SNVSAZ0C Data sheet

SNVSAZ0C March 2018 – October 2021 LM51501-Q1

PRODUCTION DATA

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

RUM|16

Thermal pad, mechanical data (Package|Pins)

RUM|16
- QFND655A

Orderable Information

7.5 Electrical Characteristics

Typical values correspond to T_J = 25°C. Minimum and maximum limits apply over T_J = –40°C to 125°C. Unless otherwise stated, V_VOUT = 9.5 V, R_T = 9.09 kΩ

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY CURRENT
I_{SHUTDOWN(VOUT)}	VOUT shutdown current	V_VOUT = 12 V, V_EN = 0 V		5	12	µA
I_{STANDBY(VOUT)}	VOUT standby current (PVCC in regulation, STATUS is low)	V_VOUT = 12 V, V_EN = 3.3 V, R_SET = 90.9 kΩ		15	25	µA
I_WAKEUP(VOUT)	VOUT operating current (exclude the current into the RT resistor)	V_VOUT = 11.5 V, V_EN = 2.5 V, nonswitching, R_T = 9.09 kΩ		1.2	2.0	mA
I_{SHUTDOWN(VIN)}	VIN shutdown current	V_VIN = 12 V, V_EN = 0 V		0.1	0.5	µA
I_STANDBY(VIN)	VIN standby current	V_VIN = 12 V, V_EN = 3.3 V, R_SET = 29.4 kΩ		0.1	0.5	µA
I_WAKEUP(VIN)	VIN operating current	V_VIN = 11.5 V, V_EN = 2.5V, nonswitching, R_T = 9.09 kΩ		30	45	µA
VCC REGULATOR
V_{VCC-REG-NOLOAD}	PVCC regulation	V_VOUT = 6.0 V, no load, wake-up mode	4.75	5	5.25	V
V_{VCC-REG-FULLLOAD}	PVCC regulation	V_VOUT = 5.0 V, I_PVCC = 70 mA	4.5	4.8		V
V_{VCC-UVLO-RISING}	AVCC UVLO threshold	AVCC rising	4.1	4.3	4.5	V
V_{VCC-UVLO-FALLING}	AVCC UVLO threshold	AVCC falling	3.9	4.1	4.3	V
V_VCC-UVLO-HYS	AVCC UVLO hysteresis			0.2		V
I_VCC-CL	PVCC sourcing current limit	V_PVCC = 0 V, wake-up mode	75			mA
ENABLE
V_EN-RISING	Enable threshold	EN rising		1.7	2	V
V_EN-FALLING	Enable threshold	EN falling	1	1.3		V
I_EN	EN bias current	V_EN = 42 V			100	nA
6.0V SETTING
V_VOUT-REG	VOUT regulation target	R_SET = 29.4 kΩ or 90.9 kΩ	5.88	6.00	6.12	V
V_VOUT-WAKEUP	VOUT wake-up threshold (V_VOUT-REG + 3%)	R_SET = 29.4 kΩ or 90.9 kΩ, VOUT falling	6.06	6.18	6.30	V
V_{VOUT-STANDBY1}	VOUT standby threshold (V_VOUT-REG + 6%, EC config)	R_SET = 90.9 kΩ, VOUT rising	6.23	6.36	6.49	V
V_{VOUT-STATUS-OFF}	VOUT status off threshold (V_VOUT-REG + 12%, EC config)	R_SET = 90.9 kΩ, VOUT rising	6.59	6.72	6.85	V
V_{VOUT-STANDBY2}	VOUT standby threshold (V_VOUT-REG + 24%, SS config)	R_SET = 29.4 kΩ, VOUT rising	7.30	7.44	7.54	V
V_VIN-STANDBY	VIN standby threshold (V_VOUT-WAKEUP + 1.0 V, SS config)	R_SET = 29.4 kΩ, VIN rising	7.04	7.18	7.32	V
6.5V SETTING
V_VOUT-REG	VOUT regulation target	R_SET = 19.1 kΩ or 71.5 kΩ	6.37	6.50	6.63	V
V_VOUT-WAKEUP	VOUT wake-up threshold (V_VOUT-REG + 3%)	R_SET = 19.1 kΩ or 71.5 kΩ, VOUT falling	6.56	6.70	6.83	V
V_{VOUT-STANDBY1}	VOUT standby threshold (V_VOUT-REG + 6%, EC config)	R_SET = 71.5 kΩ, VOUT rising	6.75	6.89	7.03	V
V_{VOUT-STATUS-OFF}	VOUT status off threshold (V_VOUT-REG + 12%, EC config)	R_SET = 71.5 kΩ, VOUT rising	7.13	7.28	7.43	V
V_{VOUT-STANDBY2}	VOUT standby threshold (V_VOUT-REG + 24%, SS config)	R_SET = 19.1 kΩ, VOUT rising	7.92	8.06	8.16	V
V_VIN-STANDBY	VIN standby threshold (V_VOUT-WAKEUP + 1.0 V, SS config)	R_SET = 19.1 kΩ, VIN rising	7.54	7.70	7.85	V
9.5V SETTING
V_VOUT-REG	VOUT regulation target	R_SET = 9.53 kΩ or 54.9 kΩ	9.31	9.50	9.69	V
V_VOUT-WAKEUP	VOUT wake-up threshold (V_VOUT-REG + 3%)	R_SET = 9.53 kΩ or 54.9 kΩ, VOUT falling	9.59	9.79	9.98	V
V_{VOUT-STANDBY1}	VOUT standby threshold (V_VOUT-REG + 6%, EC config)	R_SET = 54.9 kΩ, VOUT rising	9.87	10.07	10.27	V
V_{VOUT-STATUS-OFF}	VOUT status off threshold (V_VOUT-REG + 12%, EC config)	R_SET = 54.9 kΩ, VOUT rising	10.43	10.64	10.85	V
V_{VOUT-STANDBY2}	VOUT standby threshold (V_VOUT-REG + 24%, SS config)	R_SET = 9.53 kΩ, VOUT rising	11.55	11.78	11.95	V
V_VIN-STANDBY	VIN standby threshold (V_VOUT-WAKEUP + 1.0 V, SS mode)	R_SET = 9.53 kΩ, VIN rising	10.57	10.79	11.00	V
11.5V SETTING
V_VOUT-REG	VOUT regulation target	R_SET = GND or 41.2 kΩ	11.27	11.50	11.73	V
V_VOUT-WAKEUP	VOUT wake-up threshold (V_VOUT-REG + 3%)	R_SET = GND or 41.2 kΩ, VOUT falling	11.61	11.85	12.08	V
V_{VOUT-STANDBY1}	VOUT standby threshold (V_VOUT-REG + 6%, EC config)	R_SET = 41.2 kΩ, VOUT rising	11.95	12.19	12.43	V
V_{VOUT-STATUS-OFF}	VOUT status off threshold (V_VOUT-REG + 12%, EC config)	R_SET = 41.2 kΩ, VOUT rising	12.62	12.88	13.14	V
V_{VOUT-STANDBY2}	VOUT standby threshold (V_VOUT-REG + 24%, SS config)	R_SET = GND, VOUT rising	13.98	14.26	14.55	V
V_VIN-STANDBY	VIN standby threshold (V_VOUT-WAKEUP + 1.0 V, SS config)	R_SET = GND, VIN rising	12.52	12.85	13.10	V
RT
V_RT-REG	RT regulation voltage			1.2		V
CLOCK SYNCHRONIZATION
V_SYNC-RISING	SYNC rising threshold			2.0	2.4	V
V_SYNC-FALLING	SYNC falling threshold		0.4	1.5		V
PULSE WIDTH MODULATION AND OSCILLATOR
F_SW1	Switching frequency	R_T = 93.1 kΩ	204	239	270	kHz
F_SW2	Switching frequency	R_T = 9.09 kΩ	2100	2300	2500	kHz
F_SW3	Switching frequency	R_T = 9.09 kΩ, F_SYNC = 2.0 MHz		2000		kHz
T_ON-MIN	Forced minimum on time	SS config, V_COMP = 0 V	30	50	70	ns
D_MIN	Minimum duty cycle limit (EC config)	R_T = 9.09 kΩ, V_VIN = 1.5 V, V_VOUT = 6.5 V, V_COMP = 0 V		59		%
D_MIN	Minimum duty cycle limit (EC config)	R_T = 93.1 kΩ, V_VIN = 7.6 V, V_VOUT = 9.5 V, V_COMP = 0 V		16		%
D_MAX	Maximum duty cycle limit	SS config, R_T = 9.09 kΩ	83	87	91	%
D_MAX	Maximum duty cycle limit	EC config, R_T = 93.1 kΩ	83	87	93	%
CURRENT SENSE
V_CLTH	Current Limit threshold (CS-AGND)⁽¹⁾	V_VIN = 7.13 V, V_VOUT = 9.5 V at 25% DC	102	120	138	mV
		V_VIN = 4.75 V, V_VOUT = 9.5 V at 50% DC	102	120	138	mV
		V_VIN = 2.38 V, V_VOUT = 9.5 V at 75% DC	102	120	138	mV
ERROR AMPLIFIER
Gm	Transconductance			2		mA/V
	COMP souring current	V_COMP = 0 V	312			µA
	COMP sinking current	V_COMP = 1.5 V	120			µA
	COMP clamp voltage		2.4	2.6		V
	COMP to PWM offset			0.3		V
STATUS
	Low-state voltage drop	1-mA sinking		0.1		V
	STATUS rise to LO delay	5-kΩ pullup to 5 V	4	5	6	µs
MOSFET DRIVER
	High-state voltage drop	50-mA sinking		0.075		V
	Low-state voltage drop	50mA sourcing		0.055		V
THERMAL SHUTDOWN (TSD)
	Thermal shutdown threshold	Temperature rising		175		°C
	Thermal shutdown hysteresis			15		°C

(1) V_CL at the current limit comparator input is 10 × V_CLTH