The LMK05318 has two reference inputs, one digital PLL (DPLL), two analog PLLs (APLLs) with integrated VCOs, and eight output clocks with a RMS phase jitter of 50fs typical from APLL1 and 125fs typical from APLL2. The ultra-low jitter and high PSNR of the device can reduce bit error rates (BER) in high-speed serial links.

APLL1 uses an ultra-high performance BAW VCO (VCBO) with a very high quality factor, and thus has no dependency on the phase noise or frequency of the external oscillator (XO) input clock. This minimizes the overall design cost and allows the use of an off-the-shelf XO, TCXO, or OCXO selected to meet the free-run and holdover frequency stability requirements of the application. APLL1 is cascaded with the DPLL, allowing the APLL1 domain to be locked to the DPLL reference input for synchronous clock generation. APLL2 can be used to generate unrelated clock frequencies either locked to the APLL1 domain or the free-running XO input.

The DPLL reference input mux supports automatic input selection or manual input selection through software or pin control. The device provides hitless switching with proprietary phase cancellation for improved phase transient performance (±50ps typical). The reference clock input monitoring block monitors the clock inputs and performs a hitless switchover or holdover when a loss of reference (LOR) is detected. A LOR condition can be detected upon any violation of the threshold limits set for the input monitors, which include amplitude, frequency, missing pulse, and runt pulse. The threshold limits for each input detector can be set and enabled per clock input. The tuning word history monitor feature allows the initial output frequency accuracy upon entry into holdover to be determined by the historical average frequency when locked, minimizing the frequency and phase disturbance during a LOR condition.

The device has eight outputs with programmable drivers, allowing up to eight differential clocks, or a combination of differential clocks and up to four 1.8V LVCMOS pairs (two outputs per pair). The output clocks can be selected from either APLL/VCO domain through the output muxes. The output dividers have a SYNC feature to allow multiple outputs to be phase-aligned.

To support IEEE 1588 PTP peripheral clock or other clock steering applications, the DPLL also supports DCO mode with less than 0.001ppb (part per billion) frequency resolution for precise frequency and phase adjustment through external software or pin control.

The device is fully programmable through I²C or SPI and supports custom start-up frequency configuration with the internal EEPROM, which is factory pre-programmed and in-system programmable if needed. The clock input and PLL monitoring status can be observed through the status pins and interrupt registers for full diagnostic capability.

The DPLL supports programmable loop bandwidth for jitter and wander attenuation, while the two APLLs support fractional frequency translation for flexible clock generation. The synchronization options supported on the DPLL include hitless switching with phase cancellation, digital holdover, and DCO mode with less than 0.001ppb (part per billion) frequency step size for precision clock steering (IEEE 1588 PTP peripheral). The advanced reference input monitoring block provides robust clock fault detection and helps to minimize output clock disturbance when a loss of reference (LOR) occurs.

The device can use a commonly available low-frequency TCXO or OCXO to set the free-run or holdover output frequency stability per synchronization standards. Otherwise, the device can use a standard XO when free-run or holdover frequency stability and wander are not critical. The device is fully programmable through I²C or SPI, and supports custom frequency configuration on power up with the internal EEPROM. The EEPROM is factory pre-programmed and can be programmed in-system, if needed.