SNAS771A December 2018 – December 2018 LMK05318
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Hitless switching between 1-PPS inputs is supported when zero-delay mode (ZDM) synchronization is disabled, but the switchover event should only occur after the DPLL has acquired lock. If a switchover occurs before the DPLL has locked initially, the switchover will not be hitless and the DPLL will take an indeterminate amount of time to lock. In this case, a soft-reset should be issued for the DPLL to lock to the selected input. In an application, the system host can monitor the DPLL lock status through a STATUS pin or bit to determine when the DPLL has locked before allowing a switchover between 1-PPS inputs. The DPLL lock time is governed by the DPLL bandwidth (typically 10 mHz for a 1-PPS input).
Hitless switching between 1-PPS inputs is not supported when ZDM synchronization is enabled.