SNAS855E November   2023  – August 2025 LMKDB1102 , LMKDB1104 , LMKDB1108 , LMKDB1120

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 
    5. 6.5 Electrical Characteristics
    6. 6.6 SMBus Timing Requirements
    7. 6.7 SBI Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Features
        1. 8.3.1.1 Running Input Clocks When Device is Powered Off
        2. 8.3.1.2 Fail-Safe Inputs
        3. 8.3.1.3 Input Configurations
          1. 8.3.1.3.1 Internal Termination for Clock Inputs
          2. 8.3.1.3.2 AC-Coupled or DC-Coupled Clock Inputs
      2. 8.3.2 Flexible Power Sequence
        1. 8.3.2.1 PWRDN# Assertion and Deassertion
        2. 8.3.2.2 OE# Assertion and Deassertion
        3. 8.3.2.3 Clock Input and PWRGD/PWRDN# Behaviors When Device Power is Off
      3. 8.3.3 LOS and OE
        1. 8.3.3.1 Additional OE# Pins for LMKDB1120 and Backward Compatibility
        2. 8.3.3.2 Synchronous OE
        3. 8.3.3.3 OE Control
        4. 8.3.3.4 Automatic Output Disable
        5. 8.3.3.5 LOS Detection
      4. 8.3.4 Output Features
        1. 8.3.4.1 Double Termination
        2. 8.3.4.2 Programmable Output Slew Rate
          1. 8.3.4.2.1 Slew Rate Control through Pin
          2. 8.3.4.2.2 Slew Rate Control through SMBus
        3. 8.3.4.3 Programmable Output Swing
        4. 8.3.4.4 Accurate Output Impedance
        5. 8.3.4.5 Programmable Output Impedance
        6. 8.3.4.6 Fail-Safe Outputs
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Mode
      2. 8.4.2 SBI Mode
      3. 8.4.3 Pin Mode
  10. 9 Register Maps
    1. 9.1 LMKDB1120 and LMKDB1120FS Registers
    2. 9.2 LMKDB1108 and LMKDB1108FS Registers
    3. 9.3 LMKDB1104 and LMKDB1104FS Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 LMKDB1120 and LMKDB1120FS 6mm × 6mm NPP Package80 Pin TLGATop View
Legend
CLOCK INPUTS CLOCK OUTPUTS POWER
GND LOGIC CONTROLS / STATUS NO CONNECT
Table 5-1 LMKDB1120 and LMKDB1120FS Pin Functions
PIN TYPE(1) DESCRIPTION
NAME(2)(3) NO.
CLOCK INPUTS
CLKIN_P G1 I Differential clock input.
CLKIN_N H1 I
CLOCK OUTPUTS
CLK0_P J1 O LP-HCSL differential clock output 0. No connect if unused.
CLK0_N K1 O
CLK1_P L1 O LP-HCSL differential clock output 1. No connect if unused.
CLK1_N M1 O
CLK2_P M2 O LP-HCSL differential clock output 2. No connect if unused.
CLK2_N M3 O
CLK3_P M4 O LP-HCSL differential clock output 3. No connect if unused.
CLK3_N M5 O
CLK4_P M7 O LP-HCSL differential clock output 4. No connect if unused.
CLK4_N M8 O
CLK5_P M9 O LP-HCSL differential clock output 5. No connect if unused.
CLK5_N M10 O
CLK6_P M11 O LP-HCSL differential clock output 6. No connect if unused.
CLK6_N M12 O
CLK7_P L12 O LP-HCSL differential clock output 7. No connect if unused.
CLK7_N K12 O
CLK8_P J12 O LP-HCSL differential clock output 8. No connect if unused.
CLK8_N H12 O
CLK9_P G12 O LP-HCSL differential clock output 9. No connect if unused.
CLK9_N F12 O
CLK10_P D12 O LP-HCSL differential clock output 10. No connect if unused.
CLK10_N C12 O
CLK11_P B12 O LP-HCSL differential clock output 11. No connect if unused.
CLK11_N A12 O
CLK12_P A11 O LP-HCSL differential clock output 12. No connect if unused.
CLK12_N A10 O
CLK13_P A9 O LP-HCSL differential clock output 13. No connect if unused.
CLK13_N A8 O
CLK14_P A7 O LP-HCSL differential clock output 14. No connect if unused.
CLK14_N A6 O
CLK15_P A5 O LP-HCSL differential clock output 15. No connect if unused.
CLK15_N A4 O
CLK16_P A3 O LP-HCSL differential clock output 16. No connect if unused.
CLK16_N A2 O
CLK17_P A1 O LP-HCSL differential clock output 17. No connect if unused.
CLK17_N B1 O
CLK18_P C1 O LP-HCSL differential clock output 18. No connect if unused.
CLK18_N D1 O
CLK19_P E1 O LP-HCSL differential clock output 19. No connect if unused.
CLK19_N F1 O
POWER
VDDA H2 P Analog power supply. Additional power supply filtering is recommended. See Section 10.3 for details.
VDDCLK B2, B6, B11, L2, L11 P Output power supply
Thermal Pad (GND) Pad G Device Ground, Thermal pad.
LOGIC CONTROLS / STATUS
vOE0#/NC J2 I Active low input to control CLK0. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive
vOE1#/NC K2 I Active low input to control CLK1. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive
vOE2#/NC L3 I Active low input to control CLK2. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive
vOE3#/NC L6 I Active low input to control CLK3. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive
vOE4#/NC L9 I Active low input to control CLK4. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive
vOE5#/SBI_IN L8 I Active low input to control CLK5 or SBI data input pin. SBI_EN pin controls function of this pin. Internal pulldown resistor.

OE mode: 0 = Active output, 1 = Inactive output.

Side-Band Mode: SBI data input.
vOE6#/SBI_CLK L10 I Active low input to control CLK6 or SBI clock input pin. SBI_EN pin controls function of this pin. Internal pulldown resistor.

OE mode: 0 = Active output, 1 = Inactive output.

Side-Band Mode: SBI clock input.
vOE7# K11 I Active low input to control CLK7. Internal pulldown resistor.

0 = Output Active, 1 = Output Inactive
vOE8# H11 I Active low input to control CLK8. Internal pulldown resistor.

0 = Output Active, 1 = Output Inactive
vOE9# E12 I Active low input to control CLK9. Internal pulldown resistor.

0 = Output Active, 1 = Output Inactive
vOE10#/SHFT_LD# E11 I Active low input to control CLK10 or SBI active low shift register load pin. SBI_EN pin controls function of this pin. Internal pulldown resistor.

OE mode: 0 = Active output, 1 = Inactive output.

Side-Band Mode: SBI shift register load input.
vOE11# C11 I Active low input to control CLK11. Internal pulldown resistor.

0 = Output Active, 1 = Output Inactive
vOE12# B10 I Active low input to control CLK12. Internal pulldown resistor.

0 = Output Active, 1 = Output Inactive
vOE13#/NC B9 I Active low input to control CLK13. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive
OE14#/NC B7 I Active low input to control CLK14. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive
vOE15#/NC B5 I Active low input to control CLK15. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive
vOE16#/NC B3 I Active low input to control CLK16. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive
vOE17#/NC D2 I Active low input to control CLK17. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive
vOE18#/NC D11 I Active low input to control CLK18. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive
vOE19#/NC J11 I Active low input to control CLK19. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive
SBI_OUT/NC C2 O SBI data output pin/No connect. This pin can be left no connect to match with DB2000QL pinout.
vPWRGD/PWRDN# M6 I Power Good/Power Down Active Low. Multifunctional input pin. Internal pullup resistor.

On the first low-to-high transition, functions as Power Good pin which starts up the device

On the subsequent low/high transitions, functions as Power Down Active Low pin which controls the device to enter or exit power-down mode.

Low = power-down mode

High = normal operation mode
vSBI_EN E2 I SBI Enable. Internal pulldown resistor. Do not change the state of this pin after power-up.

Low at power-up = SBI interface disabled. Pin L8, L10 and E11 function as OE pins. High at power-up = SBI interface enabled.

Pin L8, L10 and E11 function as SBI interface pins. SMBus and other OE pins remain functional.
^vSADR1_tri B8 I SMBus Address 3-level input pin. Internal pullup and pulldown resistors.
^vSADR0_tri B4 I SMBus Address 3-level input pin. Internal pullup and pulldown resistors.
LOS#/NC G11 O Loss of Input Clock Signal Active Low/No Connect. Open drain. Requires external pullup resistor. This pin can be left no connect to match with DB2000QL pinout.

Low = Invalid input clock.

High = Valid input clock.
SMB_DATA L4 I/O SMBus Data. Requires external pullup resistor. No connect if unused.
SMB_CLK L5 I SMBus Clock. Requires external pullup resistor. No connect if unused.
NC F2, F11, G2, L7 NC No connect.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect
(2) Pins with a "^" prefix have an internal pullup resistor. Pins with a "v" prefix have an internal pulldown resistor. Pins with a "^v" have an internal pullup resistor and an internal pulldown resistor so that mid level is selected when the pin is left floating. Pins with "^/v" have an internal pullup or pulldown based on selected function.
(3) The "#" symbol indicates active low.
Figure 5-2 LMKDB1108 and LMKDB1108FS 5mm x 5mm VQFN Package40 PinTop View
Legend
CLOCK INPUTS CLOCK OUTPUTS POWER
GND LOGIC CONTROLS / STATUS NO CONNECT
Table 5-2 LMKDB1108 and LMKDB1108FS Pin Functions
PIN TYPE(1) DESCRIPTION
NAME(2)(3) NO.
CLOCK INPUTS
CLKIN_P 8 I Differential clock input.
CLKIN_N 9 I
CLOCK OUTPUTS
CLK0_P 15 O LP-HCSL differential clock output 0. No connect if unused.
CLK0_N 16 O
CLK1_P 17 O LP-HCSL differential clock output 1. No connect if unused.
CLK1_N 18 O
CLK2_P 22 O LP-HCSL differential clock output 2. No connect if unused.
CLK2_N 23 O
CLK3_P 24 O LP-HCSL differential clock output 3. No connect if unused.
CLK3_N 25 O
CLK4_P 28 O LP-HCSL differential clock output 4. No connect if unused.
CLK4_N 29 O
CLK5_P 31 O LP-HCSL differential clock output 5. No connect if unused.
CLK5_N 32 O
CLK6_P 35 O LP-HCSL differential clock output 6. No connect if unused.
CLK6_N 36 O
CLK7_P 38 O LP-HCSL differential clock output 7. No connect if unused.
CLK7_N 39 O
POWER
VDDA 7 P Analog power supply. Additional power supply filtering is recommended. See Section 10.3 for details.
VDDCLK 10, 13, 20, 26, 37, P Output power supply
Thermal Pad (GND) Pad G Device Ground, Thermal pad.
LOGIC CONTROLS / STATUS
vOE0#/SHFT_LD# 14 I Active low input to control CLK0 or SBI active low shift register load pin. SBI_EN pin controls function of this pin. Internal pulldown resistor. OE mode: 0 = Active output, 1 = Inactive output.

Side-Band Mode: SBI latch register input.
vOE1#/SBI_IN 19 I Active low input to control CLK1 or SBI data input pin. SBI_EN pin controls function of this pin. Internal pulldown resistor. OE mode: 0 = Active output, 1 = Inactive output.

Side-Band Mode: SBI data input.
vOE2# 21 I Active low input to control CLK2. Internal pulldown resistor.

0 = Output Active, 1 = Output Inactive
vOE3# 27 I Active low input to control CLK3. Internal pulldown resistor.

0 = Output Active, 1 = Output Inactive
vOE4#/SBI_CLK 30 I Active low input to control CLK4 or SBI clock input pin. SBI_EN pin controls function of this pin. Internal pulldown resistor. OE mode: 0 = Active output, 1 = Inactive output.

Side-Band Mode: SBI clock input.
vOE5# 33 I Active low input to control CLK5. Internal pulldown resistor.

0 = Output Active, 1 = Output Inactive
vOE10#/SBI_OUT 34 I or O Active low input to control CLK6 or SBI data output pin. Internal pulldown resistor. SBI_EN pin controls function of this pin.

OE mode:0 = Active output, 1 = Inactive output.

SBI Mode: SBI shift register data output.

vOE7# 40 I Active low input to control CLK7. Internal pulldown resistor.

0 = Output Active, 1 = Output Inactive
vPWRGD/PWRDN# 12 I Power Good/Power Down Active Low. Multifunctional input pin. Internal pulldown resistor.

On the first low-to-high transition, functions as Power Good pin which starts up the device

On the subsequent low/high transitions, functions as Power Down Active Low pin which controls the device to enter or exit power-down mode.

Low = power-down mode

High = normal operation mode
vSBI_EN 11 I SBI Enable. Internal pulldown resistor. Do not change the state of this pin after power-up.

Low at power-up = SBI interface disabled. Pin 20, 32, 48 and 55 function as OE pins.

High at power-up = SBI interface enabled. Pin 20, 32, 48 and 55 function as SBI interface pins. SMBus and other OE pins remain functional.
^vSADR1_tri 3 I SMBus Address 3-level input pin. Internal pullup and pulldown resistors.
^vSADR0_tri 4 I SMBus Address 3-level input pin. Internal pullup and pulldown resistors.
^SLEWRATE_SEL 2 I LP-HCSL differential clock output slew rate select pin. Internal pullup resistor.

Low = Slow slew rate.

High = Fast slew rate.
LOS# 1 O Loss of Input Clock Signal Active Low/No Connect. Open drain. Requires external pullup resistor.

Low = Invalid input clock.

High = Valid input clock.
SMB_DATA 5 I/O SMBus Data. Requires external pullup resistor. No connect if unused.
SMB_CLK 6 I SMBus Clock. Requires external pullup resistor. No connect if unused.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect
(2) Pins with a "^" prefix have an internal pullup resistor. Pins with a "v" prefix have an internal pulldown resistor. Pins with a "^v" have an internal pullup resistor and an internal pulldown resistor so that mid level is selected when the pin is left floating.
(3) The "#" symbol indicates active low.
Figure 5-3 LMKDB1104 and LMKDB1104FS 4mm x 4mm VQFN Package28 PinTop View
Legend
CLOCK INPUTS CLOCK OUTPUTS POWER
GND LOGIC CONTROLS / STATUS NO CONNECT
Table 5-3 LMKDB1104 and LMKDB1104FS Pin Functions
PIN TYPE(1) DESCRIPTION
NAME(2)(3) NO.
CLOCK INPUTS
CLKIN_P 6 I Differential clock input.
CLKIN_N 7 I
CLOCK OUTPUTS
CLK0_P 12 O LP-HCSL differential clock output 0. No connect if unused.
CLK0_N 13 O
CLK1_P 16 O LP-HCSL differential clock output 1. No connect if unused.
CLK1_N 17 O
CLK2_P 19 O LP-HCSL differential clock output 2. No connect if unused.
CLK2_N 20 O
CLK3_P 23 O LP-HCSL differential clock output 3. No connect if unused.
CLK3_N 24 O
POWER
VDDA 5 P Analog power supply. Additional power supply filtering is recommended. See Section 10.3 for details.
VDDCLK 10, 15, 18, 25 P Output power supply
Thermal Pad (GND) Pad G Device Ground, Thermal pad.
LOGIC CONTROLS / STATUS
vOE0#/SHFT_LD# 11 I Active low input to control CLK0 or SBI active low shift register load pin. SBI_EN pin controls function of this pin. Internal pulldown resistor. OE mode: 0 = Active output, 1 = Inactive output.

Side-Band Mode: SBI latch register input.
vOE1#/SBI_IN 14 I Active low input to control CLK1 or SBI data input pin. SBI_EN pin controls function of this pin. Internal pulldown resistor. OE mode: 0 = Active output, 1 = Inactive output.

Side-Band Mode: SBI data input.
vOE2#/SBI_CLK 21 I Active low input to control CLK2 or SBI clock input pin. SBI_EN pin controls function of this pin. Internal pulldown resistor. OE mode: 0 = Active output, 1 = Inactive output.

Side-Band Mode: SBI clock input.
vOE3#/SBI_OUT 22 I or O Active low input to control CLK3 or SBI data output pin. Internal pulldown resistor. SBI_EN pin controls function of this pin.

OE mode:0 = Active output, 1 = Inactive output.

SBI Mode: SBI shift register data output.

vPWRGD/PWRDN# 9 I Power Good/Power Down Active Low. Multifunctional input pin. Internal pulldown resistor.

On the first low-to-high transition, functions as Power Good pin which starts up the device

On the subsequent low/high transitions, functions as Power Down Active Low pin which controls the device to enter or exit power-down mode.

Low = power-down mode

High = normal operation mode
vSBI_EN 8 I SBI Enable. Internal pulldown resistor. Do not change the state of this pin after power-up.

Low at power-up = SBI interface disabled. Pin 20, 32, 48 and 55 function as OE pins.

High at power-up = SBI interface enabled. Pin 20, 32, 48 and 55 function as SBI interface pins. SMBus and other OE pins remain functional.
^vSADR1_tri 1 I SMBus Address 3-level input pin. Internal pullup and pulldown resistors.
^vSADR0_tri 2 I SMBus Address 3-level input pin. Internal pullup and pulldown resistors.
^SLEWRATE_SEL 27 I LP-HCSL differential clock output slew rate select pin. Internal pullup resistor.

Low = Slow slew rate.

High = Fast slew rate.
LOS# 28 O Loss of Input Clock Signal Active Low/No Connect. Open drain. Requires external pullup resistor.

Low = Invalid input clock.

High = Valid input clock.
SMB_DATA 3 I/O SMBus Data. Requires external pullup resistor. No connect if unused.
SMB_CLK 4 I SMBus Clock. Requires external pullup resistor. No connect if unused.
NC 26 NC No connect.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect
(2) Pins with a "^" prefix have an internal pullup resistor. Pins with a "v" prefix have an internal pulldown resistor. Pins with a "^v" have an internal pullup resistor and an internal pulldown resistor so that mid level is selected when the pin is left floating.
(3) The "#" symbol indicates active low.
Figure 5-4 LMKDB1102 3mm x 3mm VQFN Package20 PinTop View
Legend
CLOCK INPUTS CLOCK OUTPUTS POWER
GND LOGIC CONTROLS / STATUS NO CONNECT
Table 5-4 LMKDB1102 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME(2)(3) NO.
CLOCK INPUTS
CLKIN_P 1 I Differential clock input.
CLKIN_N 2 I
CLOCK OUTPUTS
CLK1_P 16 O LP-HCSL differential clock output 1. No connect if unused.
CLK1_N 17 O
CLK2_P 9 O LP-HCSL differential clock output 2. No connect if unused.
CLK2_N 10 O
POWER
VDDA 6 P Analog power supply. Additional power supply filtering is recommended. See Section 10.3 for details.
VDDCLK 3, 8, 14, 18, 19 P Output power supply
GND 7, 20 G Device Ground, Thermal pad.
Thermal Pad (GND) Pad G Device Ground, Thermal pad.
LOGIC CONTROLS / STATUS
^OE1# 15 I Active low input to control CLK1. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive
^OE2# 12 I Active low input to control CLK2. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive
LOS# 13 O Loss of Input Clock Signal Active Low/No Connect. Open drain. Requires external pullup resistor.

Low = Invalid input clock.

High = Valid input clock.
vZOUT_SEL 11 I LP-HCSL differential clock output impedance select. Internal pulldown resistor.

Low = 85Ω.

High = 100Ω.
NC 4, 5 NC No connect.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect
(2) Pins with a "^" prefix have an internal pullup resistor. Pins with a "v" prefix have an internal pulldown resistor. Pins with a "^v" have an internal pullup resistor and an internal pulldown resistor so that mid level is selected when the pin is left floating.
(3) The "#" symbol indicates active low.