SNAS855E November   2023  – August 2025 LMKDB1102 , LMKDB1104 , LMKDB1108 , LMKDB1120

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 
    5. 6.5 Electrical Characteristics
    6. 6.6 SMBus Timing Requirements
    7. 6.7 SBI Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Features
        1. 8.3.1.1 Running Input Clocks When Device is Powered Off
        2. 8.3.1.2 Fail-Safe Inputs
        3. 8.3.1.3 Input Configurations
          1. 8.3.1.3.1 Internal Termination for Clock Inputs
          2. 8.3.1.3.2 AC-Coupled or DC-Coupled Clock Inputs
      2. 8.3.2 Flexible Power Sequence
        1. 8.3.2.1 PWRDN# Assertion and Deassertion
        2. 8.3.2.2 OE# Assertion and Deassertion
        3. 8.3.2.3 Clock Input and PWRGD/PWRDN# Behaviors When Device Power is Off
      3. 8.3.3 LOS and OE
        1. 8.3.3.1 Additional OE# Pins for LMKDB1120 and Backward Compatibility
        2. 8.3.3.2 Synchronous OE
        3. 8.3.3.3 OE Control
        4. 8.3.3.4 Automatic Output Disable
        5. 8.3.3.5 LOS Detection
      4. 8.3.4 Output Features
        1. 8.3.4.1 Double Termination
        2. 8.3.4.2 Programmable Output Slew Rate
          1. 8.3.4.2.1 Slew Rate Control through Pin
          2. 8.3.4.2.2 Slew Rate Control through SMBus
        3. 8.3.4.3 Programmable Output Swing
        4. 8.3.4.4 Accurate Output Impedance
        5. 8.3.4.5 Programmable Output Impedance
        6. 8.3.4.6 Fail-Safe Outputs
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Mode
      2. 8.4.2 SBI Mode
      3. 8.4.3 Pin Mode
  10. 9 Register Maps
    1. 9.1 LMKDB1120 and LMKDB1120FS Registers
    2. 9.2 LMKDB1108 and LMKDB1108FS Registers
    3. 9.3 LMKDB1104 and LMKDB1104FS Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.2.2 Detailed Design Procedure

First of all, calculate the jitter budget for the clock buffer using RMS addition. The maximum allowed additive jitter for the clock buffer is square root of the difference between square of reference clock jitter and square of total clock jitter.

The maximum PCIe Gen 5 additive jitter allowed for the buffer is sqrt(502 – 452) = 21 fs. According to the Specifications under the Electrical Characteristics table, the additive PCIe Gen 5 jitter under Common Clock and ≥3.5V/ns input slew rate test condition is 13fs maximum, well below 21fs requirement. Therefore, the LMKDB1120 (20 outputs) can be used for PCIe Gen 5 clock distribution.

Similarly, the maximum 12kHz to 20MHz additive jitter allowed at 156.25MHz is sqrt(1002 – 902) = 43fs. According to the Specifications under the Electrical Characteristics table, the 12kHz to 20MHz additive jitter at 156.25MHz is 31fs maximum, well below the 43fs requirement. Therefore, the LMKDB1108 (8 outputs) can be used for Ethernet clock distribution.