SNVS829F March   1999  – May 2026 LMP8480 , LMP8481

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Theory of Operation
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  Basic Connections
      2. 7.3.2  Selection of the Sense Resistor
      3. 7.3.3  Using PCB Traces as Sense Resistors
      4. 7.3.4  VREFA and VREFB Pins (LMP8481 Only)
        1. 7.3.4.1 One-to-One (1:1) Reference Input
        2. 7.3.4.2 Setting Output to One-Half VCC or external VREF
      5. 7.3.5  Reference Input Voltage Limits (LMP8481 Only)
      6. 7.3.6  Low-Side Current Sensing
      7. 7.3.7  Input Series Resistance
      8. 7.3.8  Minimum Output Voltage
      9. 7.3.9  Swinging Output Below Ground
      10. 7.3.10 Maximum Output Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Unidirectional vs Bidirectional Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Common-Mode and Differential Voltage Range
    2. 8.2 Typical Applications
      1. 8.2.1 Unidirectional Application With the LMP8480
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Bidirectional Current Sensing Using the LMP8481
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
      3. 8.2.3 Typical Application With a Resistive Divider
  10. 9 Power Supply Recommendations
    1. 9.1 Power Supply Decoupling
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4 VREFA and VREFB Pins (LMP8481 Only)

The voltage applied to the VREFA and VREFB pins controls the output zero reference level. Depending on how the pins are configured, the output reference level can be set to GND, or VCC / 2, or external VREF / 2, or the average of two different input references.

The reference inputs consist of a pair of divider resistors with equal values to a common summing point, VREF', as shown in Figure 7-7. Assuming VSENSE is zero, the output is at the same value as VREF'.

LMP8480 LMP8481 VREF Input Resistor NetworkFigure 7-7 VREF Input Resistor Network

VREF' is the voltage at the resistor tap-point that is directly applied to the output as an offset. With the two VREF inputs tied together, the output zero voltage has a 1:1 ratio relationship with VREF.

Equation 4. VOUT = ( (VRSP – VRSN) ×Av ) + VREF’

Where:

Equation 5. VREF’ = VREFA = VREFB (Equal Inputs)

or:

Equation 6. VREF’ = ( VREFA + VREFB ) / 2 (Different Inputs)