10.1 Layout Guidelines
In general, the layout guidelines are similar to most other PLL devices. Here are some specific guidelines.
- GND pins may be routed on the package back to the DAP.
- The OSCin pins are internally biased and must be AC-coupled.
- If not used, RampClk, RampDir, and SysRefReq can be grounded to the DAP.
- For the Vtune pin, try to place a loop filter capacitor as close as possible to the pin. This may mean separating the capacitor from the rest of the loop filter.
- For the outputs, keep the pullup component as close as possible to the pin and use the same component on each side of the differential pair.
- If a single-ended output is needed, the other side must have the same loading and pullup. However, the routing for the used side can be optimized by routing the complementary side through a via to the other side of the board. On this side, use the same pullup and make the load look equivalent to the side that is used.
- Ensure that DAP on device is well-grounded with many vias, preferably copper filled.
- Have a thermal pad that is as large as the LMX2595 exposed pad. Add vias to the thermal pad to maximize thermal performance.
- Use a low loss dielectric material, such as Rogers 4003, for optimal output power.
- See instructions for the LMX2595EVM (LMX2594 EVM Instructions, 15 GHz Wideband Low Noise PLL With Integrated VCO) for more details on layout.