Product details

Integrated VCO Yes Output frequency (Min) (MHz) 100 Output frequency (Max) (MHz) 19000 Normalized PLL phase noise (dBc/Hz) -236 Current consumption (mA) 340 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -129
Integrated VCO Yes Output frequency (Min) (MHz) 100 Output frequency (Max) (MHz) 19000 Normalized PLL phase noise (dBc/Hz) -236 Current consumption (mA) 340 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -129
VQFN (RHA) 40 36 mm² 6 x 6
  • 10-MHz to 20-GHz output frequency
  • –110 dBc/Hz phase noise at 100-kHz offset with 15-GHz carrier
  • 45-fs rms jitter at 7.5 GHz (100 Hz to 100 MHz)
  • Programmable output power
  • PLL key specifications
    • Figure of merit: –236 dBc/Hz
    • Normalized 1/f noise: –129 dBc/Hz
    • High phase detector frequency
      • 400-MHz integer mode
      • 300-MHz fractional mode
    • 32-bit fractional-N divider
  • Remove integer boundary spurs with programmable input multiplier
  • Synchronization of output phase across multiple devices
  • Support for SYSREF with 9-ps resolution programmable delay
  • Frequency ramp and chirp generation ability for FMCW applications
  • < 20-µs VCO calibration speed
  • 3.3-V single power supply operation
  • 10-MHz to 20-GHz output frequency
  • –110 dBc/Hz phase noise at 100-kHz offset with 15-GHz carrier
  • 45-fs rms jitter at 7.5 GHz (100 Hz to 100 MHz)
  • Programmable output power
  • PLL key specifications
    • Figure of merit: –236 dBc/Hz
    • Normalized 1/f noise: –129 dBc/Hz
    • High phase detector frequency
      • 400-MHz integer mode
      • 300-MHz fractional mode
    • 32-bit fractional-N divider
  • Remove integer boundary spurs with programmable input multiplier
  • Synchronization of output phase across multiple devices
  • Support for SYSREF with 9-ps resolution programmable delay
  • Frequency ramp and chirp generation ability for FMCW applications
  • < 20-µs VCO calibration speed
  • 3.3-V single power supply operation

The LMX2595 high-performance, wideband synthesizer that can generate any frequency from 10 MHz to 20 GHz. An integrated doubler is used for frequencies above 15 GHz. The high-performance PLL with figure of merit of –236 dBc/Hz and high-phase detector frequency can attain very low in-band noise and integrated jitter. The high-speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. There is also a programmable input multiplier to mitigate integer boundary spurs.

The LMX2595 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. A frequency ramp generator can synthesize up to two segments of ramp in an automatic ramp generation option or a manual option for maximum flexibility. The fast calibration algorithm allows changing frequencies faster than 20 µs. The LMX2595 adds support for generating or repeating SYSREF (compliant to JESD204B standard) designed for low-noise clock sources in high-speed data converters. A fine delay adjustment (9-ps resolution) is provided in this configuration to account for delay differences of board traces.

The output drivers within LMX2595 deliver output power as high as 7 dBm at 15-GHz carrier frequency. The device runs from a single 3.3-V supply and has integrated LDOs that eliminate the need for on-board low noise LDOs.

The LMX2595 high-performance, wideband synthesizer that can generate any frequency from 10 MHz to 20 GHz. An integrated doubler is used for frequencies above 15 GHz. The high-performance PLL with figure of merit of –236 dBc/Hz and high-phase detector frequency can attain very low in-band noise and integrated jitter. The high-speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. There is also a programmable input multiplier to mitigate integer boundary spurs.

The LMX2595 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. A frequency ramp generator can synthesize up to two segments of ramp in an automatic ramp generation option or a manual option for maximum flexibility. The fast calibration algorithm allows changing frequencies faster than 20 µs. The LMX2595 adds support for generating or repeating SYSREF (compliant to JESD204B standard) designed for low-noise clock sources in high-speed data converters. A fine delay adjustment (9-ps resolution) is provided in this configuration to account for delay differences of board traces.

The output drivers within LMX2595 deliver output power as high as 7 dBm at 15-GHz carrier frequency. The device runs from a single 3.3-V supply and has integrated LDOs that eliminate the need for on-board low noise LDOs.

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Technical documentation

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Type Title Date
* Data sheet LMX2595 20-GHz Wideband PLLATINUM™ RF Synthesizer With Phase Synchronization and JESD204B Support datasheet (Rev. C) 16 Apr 2019
Application note Streamline RF Synthesizer VCO Calibration and Optimize PLL Lock Time (Rev. A) 27 Aug 2021
User guide LMX2595 EVM Instructions – 20-GHz Wideband Low Noise PLL With Integrated VCO (Rev. B) 26 Mar 2020

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMX2595EVM — 20-GHz Wideband RF Synthesizer With Phase Synchronization and JESD204B Evaluation Module

This evaluation module is for the LMX2595, which is the first PLL with integrated VCO in industry to get fundamental VCO output up to 15 GHz and up to 20 GHz with a doubler. The industry leading PLL FOM is -236 dBc/Hz with 1/f of -129 dBc/Hz. This device supports the JESD204B standard (it can (...)
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Application software & framework

PLLATINUMSIM-SW — Texas Instruments PLLatinum Simulator Tool

The PLLATINUMSIM-SW simulator tool lets you create detailed designs and simulations of our PLLATINUM™ integrated circuits which include the LMX series of PLLs and synthesizers.
Application software & framework

TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software

The TICS Pro software is used to program the evaluation modules (EVMs) for device numbers with these prefixes: CDC, LMK and LMX. These devices include PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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VQFN (RHA) 40 View options

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