SLVSBC7E October   2013  – September 2018 LMZ31530

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Efficiency
  3. 3 Description
    1.     Simplified Application
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Recommended Operating Conditions
    3. 4.3 Thermal Information
    4. 4.4 Package Specifications
    5. 4.5 Electrical Characteristics
  5. 5 Device Information
    1.     Pin Functions
    2. 5.1 Functional Block Diagram
  6. 6 Typical Characteristics (PVIN = VIN = 12 V)
  7. 7 Typical Characteristics (PVIN = VIN = 5 V)
  8. 8 Application Information
    1. 8.1  Adjusting the Output Voltage
    2. 8.2  Frequency Select
    3. 8.3  Capacitor Recommendations for the LMZ31530 Power Supply
      1. 8.3.1 Capacitor Technologies
        1. 8.3.1.1 Electrolytic, Polymer-Electrolytic Capacitors
        2. 8.3.1.2 Ceramic Capacitors
        3. 8.3.1.3 Tantalum, Polymer-Tantalum Capacitors
      2. 8.3.2 Input Capacitor
      3. 8.3.3 Output Capacitor
    4. 8.4  Transient Response
    5. 8.5  Application Curves
    6. 8.6  Application Schematics
    7. 8.7  Custom Design With WEBENCH® Tools
    8. 8.8  VIN and PVIN Input Voltage
    9. 8.9  3.3 V PVIN Operation
    10. 8.10 Power Good (PWRGD)
    11. 8.11 Slow Start (SS_SEL)
    12. 8.12 Auto-Skip Eco-mode / Forced Continuous Conduction Mode
    13. 8.13 Power-Up Characteristics
    14. 8.14 Pre-Biased Start-Up
    15. 8.15 Remote Sense
    16. 8.16 Output On/Off Inhibit (INH)
    17. 8.17 Overcurrent Protection
    18. 8.18 Current Limit (ILIM) Adjust
    19. 8.19 Thermal Shutdown
    20. 8.20 Layout Considerations
    21. 8.21 EMI
  9. 9 Revision History
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RLG|72
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.20 Layout Considerations

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 28 thru Figure 33, shows a typical PCB layout. Some considerations for an optimized layout are:

  • Use large copper areas for power planes (PVIN, VOUT, and PGND) to minimize conduction loss and thermal stress.
  • Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
  • Locate additional output capacitors between the ceramic capacitor and the load.
  • Keep AGND and PGND separate from one another. AGND should only be used as the return for RSET.
  • Place RSET, RFREQ, and RSS as close as possible to their respective pins.
  • Use multiple vias to connect the power planes to internal layers.

LMZ31530 TopLayer.pngFigure 28. Typical Top Layer Layout
LMZ31530 Layer3.pngFigure 30. Typical Layer 3 Layout
LMZ31530 Layer5.pngFigure 32. Typical Layer 5 Layout
LMZ31530 Layer2.pngFigure 29. Typical Layer 2 Layout
LMZ31530 Layer4.pngFigure 31. Typical Layer 4 Layout
LMZ31530 BOTLayerA.gifFigure 33. Typical Bottom Layer Layout