SNVSAW2B April   2017  – December 2018 LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1


  1. Features
  2. Applications
    1.     Simplified Schematic
  3. Description
    1.     Efficiency vs Output Current
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1 DC-DC Converters
        1. Overview
        2. Transition Between PWM and PFM Modes
        3. Buck Converter Load-Current Measurement
        4. Spread-Spectrum Mode
      2. 7.3.2 Sync Clock Functionality
      3. 7.3.3 Power-Up
      4. 7.3.4 Regulator Control
        1. Enabling and Disabling Regulators
        2. Changing Output Voltage
      5. 7.3.5 Enable and Disable Sequences
      6. 7.3.6 Device Reset Scenarios
      7. 7.3.7 Diagnostics and Protection Features
        1. Power-Good Information (PGOOD pin)
        2. Warnings for Diagnostics (Interrupt)
          1. Output Power Limit
          2. Thermal Warning
        3. Protection (Regulator Disable)
          1. Short-Circuit and Overload Protection
          2. Overvoltage Protection
          3. Thermal Shutdown
        4. Fault (Power Down)
          1. Undervoltage Lockout
      8. 7.3.8 GPIO Signal Operation
      9. 7.3.9 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. Data Validity
        2. Start and Stop Conditions
        3. Transferring Data
        4. I2C-Compatible Chip Address
        5. Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1.  OTP_REV
          1. Table 10. OTP_REV Register Field Descriptions
        2.  BUCK0_CTRL1
          1. Table 11. BUCK0_CTRL1 Register Field Descriptions
        3.  BUCK1_CTRL1
          1. Table 12. BUCK1_CTRL1 Register Field Descriptions
        4.  BUCK2_CTRL1
          1. Table 13. BUCK2_CTRL1 Register Field Descriptions
        5.  BUCK3_CTRL1
          1. Table 14. BUCK3_CTRL1 Register Field Descriptions
        6.  BUCK0_VOUT
          1. Table 15. BUCK0_VOUT Register Field Descriptions
        7.  BUCK0_FLOOR_VOUT
          1. Table 16. BUCK0_FLOOR_VOUT Register Field Descriptions
        8.  BUCK1_VOUT
          1. Table 17. BUCK1_VOUT Register Field Descriptions
        9.  BUCK1_FLOOR_VOUT
          1. Table 18. BUCK1_FLOOR_VOUT Register Field Descriptions
        10. BUCK2_VOUT
          1. Table 19. BUCK2_VOUT Register Field Descriptions
        11. BUCK2_FLOOR_VOUT
          1. Table 20. BUCK2_FLOOR_VOUT Register Field Descriptions
        12. BUCK3_VOUT
          1. Table 21. BUCK3_VOUT Register Field Descriptions
        13. BUCK3_FLOOR_VOUT
          1. Table 22. BUCK3_FLOOR_VOUT Register Field Descriptions
        14. BUCK0_DELAY
          1. Table 23. BUCK0_DELAY Register Field Descriptions
        15. BUCK1_DELAY
          1. Table 24. BUCK1_DELAY Register Field Descriptions
        16. BUCK2_DELAY
          1. Table 25. BUCK2_DELAY Register Field Descriptions
        17. BUCK3_DELAY
          1. Table 26. BUCK3_DELAY Register Field Descriptions
        18. GPIO2_DELAY
          1. Table 27. GPIO2_DELAY Register Field Descriptions
        19. GPIO3_DELAY
          1. Table 28. GPIO3_DELAY Register Field Descriptions
        20. RESET
          1. Table 29. RESET Register Field Descriptions
        21. CONFIG
          1. Table 30. CONFIG Register Field Descriptions
        22. INT_TOP1
          1. Table 31. INT_TOP1 Register Field Descriptions
        23. INT_TOP2
          1. Table 32. INT_TOP2 Register Field Descriptions
        24. INT_BUCK_0_1
          1. Table 33. INT_BUCK_0_1 Register Field Descriptions
        25. INT_BUCK_2_3
          1. Table 34. INT_BUCK_2_3 Register Field Descriptions
        26. TOP_STAT
          1. Table 35. TOP_STAT Register Field Descriptions
        27. BUCK_0_1_STAT
          1. Table 36. BUCK_0_1_STAT Register Field Descriptions
        28. BUCK_2_3_STAT
          1. Table 37. BUCK_2_3_STAT Register Field Descriptions
        29. TOP_MASK1
          1. Table 38. TOP_MASK1 Register Field Descriptions
        30. TOP_MASK2
          1. Table 39. TOP_MASK2 Register Field Descriptions
        31. BUCK_0_1_MASK
          1. Table 40. BUCK_0_1_MASK Register Field Descriptions
        32. BUCK_2_3_MASK
          1. Table 41. BUCK_2_3_MASK Register Field Descriptions
        33. SEL_I_LOAD
          1. Table 42. SEL_I_LOAD Register Field Descriptions
        34. I_LOAD_2
          1. Table 43. I_LOAD_2 Register Field Descriptions
        35. I_LOAD_1
          1. Table 44. I_LOAD_1 Register Field Descriptions
        36. PGOOD_CTRL1
          1. Table 45. PGOOD_CTRL1 Register Field Descriptions
        37. PGOOD_CTRL2
          1. Table 46. PGOOD_CTRL2 Register Field Descriptions
        38. PGOOD_FLT
          1. Table 47. PGOOD_FLT Register Field Descriptions
        39. PLL_CTRL
          1. Table 48. PLL_CTRL Register Field Descriptions
        40. PIN_FUNCTION
          1. Table 49. PIN_FUNCTION Register Field Descriptions
        41. GPIO_CONFIG
          1. Table 50. GPIO_CONFIG Register Field Descriptions
        42. GPIO_IN
          1. Table 51. GPIO_IN Register Field Descriptions
        43. GPIO_OUT
          1. Table 52. GPIO_OUT Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. Inductor Selection
        2. Input Capacitor Selection
        3. Output Capacitor Selection
        4. Snubber Components
        5. Supply Filtering Components
      2. 8.2.2 Current Limit vs. Maximum Output Current
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNF|26
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

The high frequency and large switching currents of the LP87524B/J/P-Q1 make the choice of layout important. Good power supply results only occur when care is given to proper design and layout. Layout affects noise pickup and generation and can cause a good design to perform with less-than-expected results. With a range of output currents from milliamps to 10 A, good power supply layout is much more difficult than most general PCB design. Use the following steps as a reference to ensure the device is stable and maintains proper voltage and current regulation across its intended operating voltage and current range.

  1. Place CIN as close as possible to the VIN_Bx pin and the PGND_Bxx pin. Route the VIN trace wide and thick to avoid IR drops. The trace between the positive node of the input capacitor and the VIN_Bx pin(s) of LP87524B/J/P-Q1, as well as the trace between the negative node of the input capacitor and power PGND_Bxx pin(s), must be kept as short as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for proper device operation. The parasitic inductance can be reduced by using a ground plane as close as possible to top layer by using thin dielectric layer between top layer and ground plane.
  2. The output filter, consisting of COUT and L, converts the switching signal at SW_Bx to the noiseless output voltage. It must be placed as close as possible to the device keeping the switch node small, for best EMI behavior. Route the traces between the LP87524B/J/P-Q1 output capacitors and the load direct and wide to avoid losses due to the IR drop.
  3. Input for analog blocks (VANA and AGND) must be isolated from noisy signals. Connect VANA directly to a quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling capacitor as close as possible to the VANA pin.
  4. If the processor load supports remote voltage sensing, connect the feedback pins FB_Bx of the LP87524B/J/P-Q1 device to the respective sense pins on the processor. The sense lines are susceptible to noise. They must be kept away from noisy signals such as PGND_Bxx, VIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I2C. Avoid both capacitive and inductive coupling by keeping the sense lines short, direct, and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. If series resistors are used for load current measurement, place them after connection of the voltage feedback.
  5. PGND_Bxx, VIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers, which are not able to withstand interference from noisy PGND_Bxx, VIN_Bx and SW_Bx.
  6. If the input voltage is above 4 V, place snubber components (capacitor and resistor) between SW_Bx and ground on all four phases. The components can be also placed to the other side of the board if there are area limitations and the routing traces can be kept short.

Due to the small package of this converter and the overall small solution size, the thermal performance of the PCB layout is important. Many system-dependent parameters such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures. Wide and thick power traces come with the ability to sink dissipated heat. This can be improved further on multi-layer PCB designs with vias to different planes. This results in reduced junction-to-ambient (RθJA) and junction-to-board (RθJB) thermal resistances and thereby reduces the device junction temperature, TJ. TI strongly recommends to perform of a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design process, by using a thermal modeling analysis software.