The power-up sequence for the LP87524B/J/P-Q1 is as follows:
- VANA (and VIN_Bx) reach minimum recommended level (VVANA > VANAUVLO).
- NRST is set to high level (or shorted to VANA). This initiates power-on-reset (POR), OTP reading and enables the system I/O interface. The I2C host must allow at least 1.2 ms before writing or reading data to the LP87524B/J/P-Q1.
- Device enters STANDBY-mode.
- The host can change the default register setting by I2C if needed.
- The regulator(s) can be enabled/disabled by ENx pin(s) and by I2C interface.