The regulators have output peak current limits. The peak current limits are described in Specifications. If the load current is increased so that the current limit is triggered, the regulator continues to regulate to the limit current level (current peak regulation, peak on every switching cycle). The voltage may decrease if the load current is higher than the average output current. If the current regulation continues for 20 µs, the LP87524B/J/P-Q1 device sets the BUCKx_ILIM_INT bit (in INT_BUCKx register) and pulls the nINT pin low. The host processor can read BUCKx_ILIM_STAT bits (in BUCKx_STAT register) to see if the regulator is still in peak current regulation mode.
If the load is so high that the output voltage decreases below a 350-mV level, the LP87524B/J/P-Q1 device disables the regulator and sets the BUCKx_SC_INT bit (in INT_BUCKx register). In addition the BUCKx_STAT bit (in BUCKx_STAT register) is set to 0. The interrupt is cleared when the host processor writes 1 to BUCKx_SC_INT bit. The overload situation is shown in Figure 14.