SLLSFQ7 November   2023 MCF8329A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 1pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Three Phase BLDC Gate Drivers
      2. 7.3.2  Gate Drive Architecture
        1. 7.3.2.1 Dead time and Cross Conduction Prevention
      3. 7.3.3  AVDD Linear Voltage Regulator
      4. 7.3.4  DVDD Voltage Regulator
        1. 7.3.4.1 AVDD Powered VREG
        2. 7.3.4.2 External Supply for VREG
        3. 7.3.4.3 External MOSFET for VREG Supply
      5. 7.3.5  Low-Side Current Sense Amplifier
      6. 7.3.6  Device Interface Modes
        1. 7.3.6.1 Interface - Control and Monitoring
        2. 7.3.6.2 I2C Interface
      7. 7.3.7  Motor Control Input Options
        1. 7.3.7.1 Analog-Mode Motor Control
        2. 7.3.7.2 PWM-Mode Motor Control
        3. 7.3.7.3 Frequency-Mode Motor Control
        4. 7.3.7.4 I2C based Motor Control
        5. 7.3.7.5 Input Control Reference Profiles
          1. 7.3.7.5.1 Linear Control Profiles
          2. 7.3.7.5.2 Staircase Control Profiles
          3. 7.3.7.5.3 Forward-Reverse Profiles
        6. 7.3.7.6 Control Input Transfer Function without Profiler
      8. 7.3.8  Bootstrap Capacitor Initial Charging
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed loop accelerate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Power Loop
        5. 7.3.11.5 Modulation Index Control
      12. 7.3.12 Maximum Torque Per Ampere (MTPA) Control
      13. 7.3.13 Flux Weakening Control
      14. 7.3.14 Motor Parameters
        1. 7.3.14.1 Motor Resistance
        2. 7.3.14.2 Motor Inductance
        3. 7.3.14.3 Motor Back-EMF constant
      15. 7.3.15 Motor Parameter Extraction Tool (MPET)
      16. 7.3.16 Anti-Voltage Surge (AVS)
      17. 7.3.17 Output PWM Switching Frequency
      18. 7.3.18 Active Braking
      19. 7.3.19 Dead Time Compensation
      20. 7.3.20 Voltage Sense Scaling
      21. 7.3.21 Motor Stop Options
        1. 7.3.21.1 Coast (Hi-Z) Mode
        2. 7.3.21.2 Recirculation Mode
        3. 7.3.21.3 Low-Side Braking
        4. 7.3.21.4 Active Spin-Down
      22. 7.3.22 FG Configuration
        1. 7.3.22.1 FG Output Frequency
        2. 7.3.22.2 FG in Open-Loop
        3. 7.3.22.3 FG During Motor Stop
        4. 7.3.22.4 FG Behaviour During Fault
      23. 7.3.23 DC Bus Current Limit
      24. 7.3.24 Protections
        1. 7.3.24.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.24.2  AVDD Power on Reset (AVDD_POR)
        3. 7.3.24.3  GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.24.4  BST Undervoltage Lockout (BST_UV)
        5. 7.3.24.5  MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 7.3.24.6  VSENSE Overcurrent Protection (SEN_OCP)
        7. 7.3.24.7  Thermal Shutdown (OTSD)
        8. 7.3.24.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.24.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.24.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.24.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.24.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1001b to 1111b)
        9. 7.3.24.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.24.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.24.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.24.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.24.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 7.3.24.10 Motor Lock (MTR_LCK)
          1. 7.3.24.10.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.24.10.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.24.10.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.24.10.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        11. 7.3.24.11 Motor Lock Detection
          1. 7.3.24.11.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.24.11.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.24.11.3 Lock3: No-Motor Fault (NO_MTR)
        12. 7.3.24.12 MPET Faults
        13. 7.3.24.13 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF - Gate Driver Shutdown Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Amplifier Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Operation
        3. 7.6.2.3 I2C Read Operation
        4. 7.6.2.4 Examples of I2C Communication Protocol Packets
        5. 7.6.2.5 Internal Buffers
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Internal_Algorithm_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Fault_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 Algorithm_Control Registers
      3. 7.8.3 System_Status Registers
      4. 7.8.4 Device_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1.      Detailed Design Procedure
      2.      Bootstrap Capacitor and GVDD Capacitor Selection
      3. 8.2.1 Selection of External MOSFET for VREG Power Supply
      4.      Gate Drive Current
      5.      Gate Resistor Selection
      6.      System Considerations in High Power Designs
      7.      Capacitor Voltage Ratings
      8.      External Power Stage Components
      9. 8.2.2 Application curves
        1. 8.2.2.1 Motor startup
        2.       High speed (1.8 kHz) operation
        3.       Active Braking for faster deceleration
        4. 8.2.2.2 Dead Time compensation
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7.3 Hardware_Configuration Registers

Table 7-34 lists the memory-mapped registers for the Hardware_Configuration registers. All register offset addresses not listed in Table 7-34 should be considered as reserved locations and the register contents should not be modified.

Table 7-34 HARDWARE_CONFIGURATION Registers
OffsetAcronymRegister NameSection
A4hPIN_CONFIGHardware Pin ConfigurationSection 7.7.3.1
A6hDEVICE_CONFIG1Device configuration1Section 7.7.3.2
A8hDEVICE_CONFIG2Device configuration2Section 7.7.3.3
AAhPERI_CONFIG1Peripheral Configuration1Section 7.7.3.4
AChGD_CONFIG1Gate Driver Configuration1Section 7.7.3.5
AEhGD_CONFIG2Gate Driver Configuration2Section 7.7.3.6

Complex bit access types are encoded to fit into small table cells. Table 7-35 shows the codes that are used for access types in this section.

Table 7-35 Hardware_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.7.3.1 PIN_CONFIG Register (Offset = A4h) [Reset = 00000000h]

PIN_CONFIG is shown in Table 7-36.

Return to the Summary Table.

Register to configure hardware pins

Table 7-36 PIN_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-28FLUX_WEAKENING_CURRENT_RATIOR/W0h Max value of Flux Weakening Current Reference as % of ILIMIT
0h = Only circular limit in place
1h = 80%
2h = 70%
3h = 60%
4h = 50%
5h = 40%
6h = 30%
7h = 20%
27VdcFilterDisableR/W0h Vdc filter disable
0h = Vdc filter Enable
1h = Vdc filter Disable
26-22LEAD_ANGLER/W0h Lead Angle (deg)
0- 15 = 1 × Bit Value
15 - 31 = 2 × (Bit Value -15) + 15
21-11MAX_POWERR/W0h Maximum power (Watts)
0- 1023 = 1 × Bit Value
1024 - 2047 = 2 × (Bit Value -1024) + 1024
10-9FG_IDLE_CONFIGR/W0h FG Configuration During Stop
0h = FG continues and end state not defined, provided FG_CONFIG (defining FG during coasting)
1h = FG is Hi-Z (Externally Pulled up)
2h = FG is pulled to Low
3h = FG is Hi-Z (Externally Pulled up)
8-7FG_FAULT_CONFIGR/W0h FG signal behavior during fault
0h = FG is Hi-Z (Externally Pulled up)
1h = FG is Hi-Z (Externally Pulled up)
2h = FG is pulled to Low
3h = FG active till BEMF drops below BEMF threshold defined by FG_BEMF_THR if FG_CONFIG is1
6RESERVEDR/W0h Reserved
5BRAKE_PIN_MODER/W0h Brake Pin Mode
0h = Low side Brake
1h = Reserved
4RESERVEDR/W0h Reserved
3-2BRAKE_INPUTR/W0h Brake pin override
0h = Hardware Pin BRAKE
1h = Override pin and brake according to BRAKE_PIN_MODE
2h = Override pin and do not brake / align
3h = Hardware Pin BRAKE
1-0SPEED_MODER/W0h Configure Reference Command mode from Speed pin
0h = Analog Mode
1h = Controlled by Duty Cycle of SPEED Input Pin
2h = Register Override mode
3h = Controlled by Frequency of SPEED Input Pin

7.7.3.2 DEVICE_CONFIG1 Register (Offset = A6h) [Reset = 00000000h]

DEVICE_CONFIG1 is shown in Table 7-37.

Return to the Summary Table.

Register to configure device

Table 7-37 DEVICE_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30MTPA_ENR/W0h Enable Maximum Torque Per Ampere Operation
0h = MTPA disabled
1h = MTPA enabled
29-28DAC_SOX_ANA_CONFIGR/W0h Pin 33 configuration
0h = DACOUT
1h = CSA_OUT
2h = ANA_ON_PIN
3h = CSA_OUT
27RESERVEDR/W0h Reserved
26-20I2C_SLAVE_ADDRR/W0h I2C slave address
19-5RESERVEDR/W0h Reserved
4-3SLEW_RATE_I2C_PINSR/W0h Slew Rate Control for I2C Pins
0h = 4.8 mA
1h = 3.9 mA
2h = 1.86 mA
3h = 30.8 mA
2PULLUP_ENABLER/W0h Internal Pull up Enable for nFault and FG Pins
0h = Disable
1h = Enable
1-0BUS_VOLTR/W0h Maximum DC Bus Voltage Configuration (V)
0h = 15 V
1h = 30 V
2h = 60 V
3h = Not defined

7.7.3.3 DEVICE_CONFIG2 Register (Offset = A8h) [Reset = 00000000h]

DEVICE_CONFIG2 is shown in Table 7-38.

Return to the Summary Table.

Register to configure device

Table 7-38 DEVICE_CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-16INPUT_MAXIMUM_FREQR/W0h Input frequency on speed pin for control mode as "controlled by frequency speed pin input" that corresponds to 100% duty cycle
Input duty cycle = Input frequency / INPUT_MAXIMUM_FREQ
15-14SLEEP_ENTRY_TIMER/W0h Device enters sleep mode when input source is held at or below the sleep entry threshold for SLEEP_ENTRY_TIME
0h = Sleep entry when SPEED pin remains low for 50µs
1h = Sleep entry when SPEED pin remains low for 200µs
2h = Sleep entry when SPEED pin remains low for 20ms
3h = Sleep entry when SPEED pin remains low for 200ms
13RESERVEDR/W0h Reserved
12DYNAMIC_VOLTAGE_GAIN_ENR/W0h Adjust voltage gain at 1ms rate for optimal voltage resolution at all voltage levels
0h = Dynamic Voltage Gain is Disabled
1h = Dynamic Voltage Gain is Enabled
11DEV_MODER/W0h Device mode select
0h = Standby Mode
1h = Sleep Mode
10-9CLK_SELR/W0h Clock Source
0h = Internal Oscillator
1h = N/A
2h = NA
3h = External Clock input
8EXT_CLK_ENR/W0h Enable External Clock mode
0h = Disable
1h = Enable
7-5EXT_CLK_CONFIGR/W0h External Clock Configuration
0h = 8KHz
1h = 16KHz
2h = 32KHz
3h = 64KHz
4h = 128 KHz
5h = 256 KHz
6h = 512KHz
7h = 1024 KHz
4EXT_WD_ENR/W0h Enable external Watch Dog
0h = Disable
1h = Enable
3-2EXT_WD_CONFIGR/W0h External Watchdog Configuration in I2C mode
0h = 1s
1h = 2s
2h = 5s
3h = 10s
1RESERVEDR/W0h Reserved
0EXT_WD_FAULT_MODER/W0h External Watchdog Fault Mode
0h = Report Only
1h = Latch with Hi-z

7.7.3.4 PERI_CONFIG1 Register (Offset = AAh) [Reset = 40000000h]

PERI_CONFIG1 is shown in Table 7-39.

Return to the Summary Table.

Register to peripheral1

Table 7-39 PERI_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30SPREAD_SPECTRUM_MODULATION_DISR/W1h Spread Spectrum Modulation Disable
0h = SSM is Enabled
1h = SSM is Disabled
29-26DIG_DEAD_TIMER/W0h Dead time
0h = 0
1h = 50 ns
2h = 100 ns
3h = 150 ns
4h = 200 ns
5h = 250 ns
6h = 300 ns
7h = 350 ns
8h = 400 ns
9h = 450 ns
Ah = 500 ns
Bh = 600 ns
Ch = 700 ns
Dh = 800 ns
Eh = 900 ns
Fh = 1000 ns
25-22BUS_CURRENT_LIMITR/W0h Bus Current Limit (% of BASE_CURRENT)
0h = 5 %
1h = 10 %
2h = 15 %
3h = 20 %
4h = 25 %
5h = 30 %
6h = 40 %
7h = 50 %
8h = 60 %
9h = 65 %
Ah = 70 %
Bh = 75 %
Ch = 80 %
Dh = 85 %
Eh = 90 %
Fh = 95 %
21BUS_CURRENT_LIMIT_ENABLER/W0h Bus Current Limit Enable
0h = Disable
1h = Enable
20-19DIR_INPUTR/W0h DIR pin override
0h = Hardware Pin DIR
1h = Override DIR pin with clockwise rotation OUTA-OUTB-OUTC
2h = Override DIR pin with counter clockwise rotation OUTA-OUTC-OUTB
3h = Hardware Pin DIR
18DIR_CHANGE_MODER/W0h Response to change of DIR pin status
0h = Follow motor stop options and ISD routine on detecting DIR change
1h = Change the direction through Reverse Drive while continuously driving the motor
17RESERVEDR/W0h Reserved
16-13ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRYR/W0h Speed Reference difference(% of MAX_SPEED) to enter Active Brake state
0h = 2.5%
1h = 5%
2h = 10%
3h = 15%
4h = 20%
5h = 25%
6h = 30%
7h = 35%
8h = 40%
9h = 45%
Ah = 50%
Bh = 60%
Ch = 70%
Dh = 80%
Eh = 90%
Fh = 100%
12-10ACTIVE_BRAKE_MOD_INDEX_LIMITR/W0h Modulation Index limit below which active braking will be applied
0h = 0%
1h = 40%
2h = 50%
3h = 60%
4h = 70%
5h = 80%
6h = 90%
7h = 100%
9SPD_RANGE_SELECTR/W0h SPEED/WAKE pin PWM input frequency selection
0h = 325Hz to 100KHz speed PWM input
1h = 10Hz to 325Hz speed PWM input
8RESERVEDR/W0h Reserved
7-6FLUX_WEAKENING_REFERENCER/W0h Modulation Index Reference to be tracked in Flux Weakening mode
0h = 70%
1h = 80%
2h = 90%
3h = 95%
5-4CTRL_MODER/W0h Control mode
0h = Speed Control
1h = Power Control
2h = Current Control
3h = Modulation index Control
3-0SALIENCY_PERCENTAGER/W0h Saliency Percentage calculated as ((Lq-Ld) × 100)/(4 × (Lq+Ld))

7.7.3.5 GD_CONFIG1 Register (Offset = ACh) [Reset = 00000000h]

GD_CONFIG1 is shown in Table 7-40.

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Register to configure gated driver settings1

Table 7-40 GD_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-26RESERVEDR/W0h Reserved
25-24BST_CHRG_TIMER/W0h Bootstrap Capacitor Charging Time
0h = 0 ms
1h = 3 ms
2h = 6 ms
3h = 12 ms
23SNS_FLT_MODER/W0h Sense Over Current Fault Mode
0h = Latch Mode
1h = Retry after tLCK_RETRY
22VDS_FLT_MODER/W0h VDS Over Current Fault Mode
0h = Latch Mode
1h = Retry after tLCK_RETRY
21BST_UV_MODER/W0h BST Under Voltage Fault Mode
0h = Latch Mode
1h = Retry after tLCK_RETRY
20GVDD_UV_MODER/W0h GVDD Under Voltage Fault Mode
0h = Latch Mode
1h = Retry after tLCK_RETRY
19RESERVEDR/W0h Reserved
18RESERVEDR/W0h Reserved
17RESERVEDR/W0h Reserved
16DIS_BST_FLTR/W0h Disable BST Fault
0h = Enable BST Fault
1h = Disable BST Fault
15OTS_AUTO_RECOVERYR/W0h OTS Auto recovery
0h = OTS Latched Fault
1h = OTS Auto Recovery
14-10RESERVEDR/W0h Reserved
9DIS_SNS_FLTR/W0h Disable Sense Fault
0h = Enable SNS OCP Fault
1h = Disable SNS OCP Fault
8DIS_VDS_FLTR/W0h Disable VDS Fault
0h = Enable VDS Fault
1h = Disable VDS Fault
7RESERVEDR/W0h Reserved
6-3SEL_VDS_LVLR/W0h Select the VDS_OCP Levels
0h = 0.06 V
1h = 0.12 V
2h = 0.18 V
3h = 0.24 V
4h = 0.3 V
5h = 0.36 V
6h = 0.42 V
7h = 0.48 V
8h = 0.6 V
9h = 0.8 V
Ah = 1.0 V
Bh = 1.2 V
Ch = 1.4 V
Dh = 1.6 V
Eh = 1.8 V
Fh = 2.0 V
2RESERVEDR/W0h Reserved
1-0CSA_GAINR/W0h Current Sense Amplifier (CSA) Gain
0h = 5 V/V
1h = 10 V/V
2h = 20 V/V
3h = 40 V/V

7.7.3.6 GD_CONFIG2 Register (Offset = AEh) [Reset = 00000000h]

GD_CONFIG2 is shown in Table 7-41.

Return to the Summary Table.

Register to configure gated driver settings2

Table 7-41 GD_CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-15RESERVEDR/W0h Reserved
14-0BASE_CURRENTR/W0h Base current (15 bit value) calculated based on gain settings
Base Current in Ampere = 1.5/(RSENSE × CSA_GAIN)
BASE_CURRENT = Base Current in Ampere × 32768/1200
Example: for 15A, enter 15 × 32768 / 1200