SLLSFQ7 Data sheet

SLLSFQ7 November 2023 MCF8329A

PRODUCTION DATA

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Mechanical Data (Package|Pins)

REE|36
- MPQF647

Thermal pad, mechanical data (Package|Pins)

Orderable Information

7.7.1 Algorithm_Configuration Registers

Table 7-14 lists the memory-mapped registers for the Algorithm_Configuration registers. All register offset addresses not listed in Table 7-14 should be considered as reserved locations and the register contents should not be modified.

Table 7-14 ALGORITHM_CONFIGURATION Registers

Offset	Acronym	Register Name	Section
80h	ISD_CONFIG	ISD Configuration	Section 7.7.1.1
82h	REV_DRIVE_CONFIG	Reverse Drive Configuration	Section 7.7.1.2
84h	MOTOR_STARTUP1	Motor Startup Configuration1	Section 7.7.1.3
86h	MOTOR_STARTUP2	Motor Startup Configuration2	Section 7.7.1.4
88h	CLOSED_LOOP1	Close Loop Configuration1	Section 7.7.1.5
8Ah	CLOSED_LOOP2	Close Loop Configuration2	Section 7.7.1.6
8Ch	CLOSED_LOOP3	Close Loop Configuration3	Section 7.7.1.7
8Eh	CLOSED_LOOP4	Close Loop Configuration4	Section 7.7.1.8
94h	REF_PROFILES1	Reference Profile Configuration1	Section 7.7.1.9
96h	REF_PROFILES2	Reference Profile Configuration2	Section 7.7.1.10
98h	REF_PROFILES3	Reference Profile Configuration3	Section 7.7.1.11
9Ah	REF_PROFILES4	Reference Profile Configuration4	Section 7.7.1.12
9Ch	REF_PROFILES5	Reference Profile Configuration5	Section 7.7.1.13
9Eh	REF_PROFILES6	Reference Profile Configuration6	Section 7.7.1.14

Complex bit access types are encoded to fit into small table cells. Table 7-15 shows the codes that are used for access types in this section.

Table 7-15 Algorithm_Configuration Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

7.7.1.1 ISD_CONFIG Register (Offset = 80h) [Reset = 00000000h]

ISD_CONFIG is shown in Table 7-16.

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Table 7-16 ISD_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30	ISD_EN	R/W	0h	ISD Enable 0h = Disable 1h = Enable
29	BRAKE_EN	R/W	0h	Brake enable during MSS 0h = Disable 1h = Enable
28	HIZ_EN	R/W	0h	Hi-Z enable during MSS 0h = Disable 1h = Enable
27	RVS_DR_EN	R/W	0h	Reverse Drive Enable 0h = Disable 1h = Enable
26	RESYNC_EN	R/W	0h	Resynchronization Enable 0h = Disable 1h = Enable
25-22	FW_DRV_RESYN_THR	R/W	0h	Minimum Speed threshold to resynchronize to close loop (% of MAX_SPEED) 0h = 5% 1h = 10% 2h = 15% 3h = 20% 4h = 25% 5h = 30% 6h = 35% 7h = 40% 8h = 45% 9h = 50% Ah = 55% Bh = 60% Ch = 70% Dh = 80% Eh = 90% Fh = 100%
21	RESERVED	R/W	0h	Reserved
20-17	SINGLE_SHUNT_BLANKING_TIME	R/W	0h	Blanking time before current is sampled from the PWM Edge 0h = 0.25 µs 1h = 0.5 µs 2h = 0.75 µs 3h = 1 µs 4h = 1.25 µs 5h = 1.5 µs 6h = 1.75 µs 7h = 2 µs 8h = 2.25 µs 9h = 2.5 µs Ah = 2.75 µs Bh = 3 µs Ch = 3.5 µs Dh = 4 µs Eh = 5 µs Fh = 6 µs
16-13	BRK_TIME	R/W	0h	Brake time during MSS 0h = 10 ms 1h = 50 ms 2h = 100 ms 3h = 200 ms 4h = 300 ms 5h = 400 ms 6h = 500 ms 7h = 750 ms 8h = 1 s 9h = 2 s Ah = 3 s Bh = 4 s Ch = 5 s Dh = 7.5 s Eh = 10 s Fh = 15 s
12-9	HIZ_TIME	R/W	0h	Hi-Z time during MSS 0h = 10 ms 1h = 50 ms 2h = 100 ms 3h = 200 ms 4h = 300 ms 5h = 400 ms 6h = 500 ms 7h = 750 ms 8h = 1 s 9h = 2 s Ah = 3 s Bh = 4 s Ch = 5 s Dh = 7.5 s Eh = 10 s Fh = 15 s
8-6	STAT_DETECT_THR	R/W	0h	BEMF threshold to detect if motor is stationary 0h = 100 mV 1h = 150 mV 2h = 200 mV 3h = 500 mV 4h = 1000 mV 5h = 1500 mV 6h = 2000 mV 7h = 3000 mV
5-2	REV_DRV_HANDOFF_THR	R/W	0h	Speed threshold used to transition to open loop during reverse drive (% of MAX_SPEED) 0h = 2.5% 1h = 5% 2h = 7.5% 3h = 10% 4h = 12.5% 5h = 15% 6h = 20% 7h = 25% 8h = 30% 9h = 40% Ah = 50% Bh = 60% Ch = 70% Dh = 80% Eh = 90% Fh = 100%
1-0	REV_DRV_OPEN_LOOP_CURRENT	R/W	0h	Open loop current limit during reverse drive (% of BASE_CURRENT) 0h = 15% 1h = 25% 2h = 35% 3h = 50%

7.7.1.2 REV_DRIVE_CONFIG Register (Offset = 82h) [Reset = 00000000h]

REV_DRIVE_CONFIG is shown in Table 7-17.

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Table 7-17 REV_DRIVE_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-27	REV_DRV_OPEN_LOOP_ACCEL_A1	R/W	0h	Open loop acceleration coefficient A1 during reverse drive 0h = 0.01 Hz/s 1h = 0.05 Hz/s 2h = 1 Hz/s 3h = 2.5 Hz/s 4h = 5 Hz/s 5h = 10 Hz/s 6h = 25 Hz/s 7h = 50 Hz/s 8h = 75 Hz/s 9h = 100 Hz/s Ah = 250 Hz/s Bh = 500 Hz/s Ch = 750 Hz/s Dh = 1000 Hz/s Eh = 5000 Hz/s Fh = 10000 Hz/s
26-23	REV_DRV_OPEN_LOOP_ACCEL_A2	R/W	0h	Open loop acceleration coefficient A2 during reverse drive 0h = 0.0 Hz/s2 1h = 0.05 Hz/s2 2h = 1 Hz/s2 3h = 2.5 Hz/s2 4h = 5 Hz/s2 5h = 10 Hz/s2 6h = 25 Hz/s2 7h = 50 Hz/s2 8h = 75 Hz/s2 9h = 100 Hz/s2 Ah = 250 Hz/s2 Bh = 500 Hz/s2 Ch = 750 Hz/s2 Dh = 1000 Hz/s2 Eh = 5000 Hz/s2 Fh = 10000 Hz/s2
22-20	ACTIVE_BRAKE_CURRENT_LIMIT	R/W	0h	Bus current limit during active braking (% of BASE_CURRENT) 0h = 10% 1h = 20 % 2h = 30 % 3h = 40 % 4h = 50 % 5h = 60 % 6h = 70 % 7h = 80 %
19-10	ACTIVE_BRAKE_KP	R/W	0h	10-bit value for active braking PI loop Kp. Kp = ACTIVE_BRAKE_KP / 2⁷
9-0	ACTIVE_BRAKE_KI	R/W	0h	10-bit value for active braking PI loop Ki. Ki = ACTIVE_BRAKE_KI / 2⁹

7.7.1.3 MOTOR_STARTUP1 Register (Offset = 84h) [Reset = 00000000h]

MOTOR_STARTUP1 is shown in Table 7-18.

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Table 7-18 MOTOR_STARTUP1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-29	MTR_STARTUP	R/W	0h	Motor startup option 0h = Align 1h = Double Align 2h = IPD 3h = Slow first cycle
28-25	ALIGN_SLOW_RAMP_RATE	R/W	0h	Align, slow first cycle and open loop current ramp rate 0h = 1 A/s 1h = 5 A/s 2h = 10 A/s 3h = 25 A/s 4h = 50 A/s 5h = 100 A/s 6h = 150 A/s 7h = 250 A/s 8h = 500 A/s 9h = 1000 A/s Ah = 2000 A/s Bh = 5000 A/s Ch = 10000 A/s Dh = 20000 A/s Eh = 50000 A/s Fh = No Limit A/s
24-21	ALIGN_TIME	R/W	0h	Align time 0h = 10 ms 1h = 50 ms 2h = 100 ms 3h = 200 ms 4h = 300 ms 5h = 400 ms 6h = 500 ms 7h = 750 ms 8h = 1 s 9h = 1.5 s Ah = 2 s Bh = 3 s Ch = 4 s Dh = 5 s Eh = 7.5 s Fh = 10 s
20-17	ALIGN_OR_SLOW_CURRENT_ILIMIT	R/W	0h	Align or slow first cycle current limit (% of BASE_CURRENT) 0h = 5 % 1h = 10 % 2h = 15 % 3h = 20 % 4h = 25 % 5h = 30 % 6h = 40 % 7h = 50 % 8h = 60 % 9h = 65 % Ah = 70 % Bh = 75 % Ch = 80 % Dh = 85 % Eh = 90 % Fh = 95 %
16-14	IPD_CLK_FREQ	R/W	0h	IPD Clock Frequency 0h = 50 Hz 1h = 100 Hz 2h = 250 Hz 3h = 500 Hz 4h = 1000 Hz 5h = 2000 Hz 6h = 5000 Hz 7h = 10000 Hz
13-9	IPD_CURR_THR	R/W	0h	IPD Current Threshold (% of BASE_CURRENT) 0h = 2.5 % 1h = 5 % 2h = 7.5 % 3h = 10 % 4h = 12.5 % 5h = 15 % 6h = 20 % 7h = 25 % 8h = 30 % 9h = 36.67 % Ah = 40 % Bh = 46.67 % Ch = 53..33 % Dh = 60 % Eh = 66.67 % Fh = 72 % 10h = NA 11h = NA 12h = NA 13h = NA 14h = NA 15h = NA 16h = NA 17h = NA 18h = NA 19h = NA 1Ah = NA 1Bh = NA 1Ch = NA 1Dh = NA 1Eh = NA 1Fh = NA
8	RESERVED	R/W	0h	Reserved
7-6	IPD_ADV_ANGLE	R/W	0h	IPD advance angle 0h = 0° 1h = 30° 2h = 60° 3h = 90°
5-4	IPD_REPEAT	R/W	0h	Number of times IPD is executed 0h = 1 time 1h = average of 2 times 2h = average of 3 times 3h = average of 4 times
3	OL_ILIMIT_CONFIG	R/W	0h	Open loop current limit configuration 0h = Open loop current limit defined by OL_ILIMIT 1h = Open loop current limit defined by ILIMIT
2	IQ_RAMP_DOWN_EN	R/W	0h	Iq ramp down for transition from open loop to closed loop 0h = Disable Iq ramp down 1h = Enable Iq ramp down
1	ACTIVE_BRAKE_EN	R/W	0h	Enable active braking during deceleration 0h = Disable Active Brake 1h = Enable Active Brake
0	REV_DRV_CONFIG	R/W	0h	Open loop Configuration setting for reverse drive 0h = Open loop current, A1, A2 based on forward drive 1h = Open loop current, A1, A2 based on reverse drive

7.7.1.4 MOTOR_STARTUP2 Register (Offset = 86h) [Reset = 00000000h]

MOTOR_STARTUP2 is shown in Table 7-19.

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Table 7-19 MOTOR_STARTUP2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-27	OL_ILIMIT	R/W	0h	Open Loop current limit (% of BASE_CURRENT) 0h = 5 % 1h = 10 % 2h = 15 % 3h = 20 % 4h = 25 % 5h = 30 % 6h = 40 % 7h = 50 % 8h = 60 % 9h = 65 % Ah = 70 % Bh = 75 % Ch = 80 % Dh = 85 % Eh = 90 % Fh = 95 %
26-23	OL_ACC_A1	R/W	0h	Open loop acceleration coefficient A1 0h = 0.01 Hz/s 1h = 0.05 Hz/s 2h = 1 Hz/s 3h = 2.5 Hz/s 4h = 5 Hz/s 5h = 10 Hz/s 6h = 25 Hz/s 7h = 50 Hz/s 8h = 75 Hz/s 9h = 100 Hz/s Ah = 250 Hz/s Bh = 500 Hz/s Ch = 750 Hz/s Dh = 1000 Hz/s Eh = 5000 Hz/s Fh = 10000 Hz/s
22-19	OL_ACC_A2	R/W	0h	Open loop acceleration coefficient A2 0h = 0.0 Hz/s2 1h = 0.05 Hz/s2 2h = 1 Hz/s2 3h = 2.5 Hz/s2 4h = 5 Hz/s2 5h = 10 Hz/s2 6h = 25 Hz/s2 7h = 50 Hz/s2 8h = 75 Hz/s2 9h = 100 Hz/s2 Ah = 250 Hz/s2 Bh = 500 Hz/s2 Ch = 750 Hz/s2 Dh = 1000 Hz/s2 Eh = 5000 Hz/s2 Fh = 10000 Hz/s2
18	AUTO_HANDOFF_EN	R/W	0h	Auto Handoff Enable 0h = Disable Auto Handoff (and use OPN_CL_HANDOFF_THR) 1h = Enable Auto Handoff
17-13	OPN_CL_HANDOFF_THR	R/W	0h	Open to Close loop Handoff Threshold (% of MAX_SPEED) 0h = 1% 1h = 2% 2h = 3% 3h = 4% 4h = 5% 5h = 6% 6h = 7% 7h = 8% 8h = 9% 9h = 10% Ah = 11% Bh = 12% Ch = 13% Dh = 14% Eh = 15% Fh = 16% 10h = 17% 11h = 18% 12h = 19% 13h = 20% 14h = 22.5% 15h = 25% 16h = 27.5% 17h = 30% 18h = 32.5% 19h = 35% 1Ah = 37.5% 1Bh = 40% 1Ch = 42.5% 1Dh = 45% 1Eh = 47.5% 1Fh = 50%
12-8	ALIGN_ANGLE	R/W	0h	Align Angle 0h = 0 deg 1h = 10 deg 2h = 20 deg 3h = 30 deg 4h = 45 deg 5h = 60 deg 6h = 70 deg 7h = 80 deg 8h = 90 deg 9h = 110 deg Ah = 120 deg Bh = 135 deg Ch = 150 deg Dh = 160 deg Eh = 170 deg Fh = 180 deg 10h = 190 deg 11h = 210 deg 12h = 225 deg 13h = 240 deg 14h = 250 deg 15h = 260 deg 16h = 270 deg 17h = 280 deg 18h = 290 deg 19h = 315 deg 1Ah = 330 deg 1Bh = 340 deg 1Ch = 350 deg 1Dh = Reserved 1Eh = Reserved 1Fh = Reserved
7-4	SLOW_FIRST_CYC_FREQ	R/W	0h	Frequency of first cycle in slow first cycle startup (% of MAX_SPEED) 0h = 0.1% 1h = 0.2% 2h = 0.3% 3h = 0.4% 4h = 0.5% 5h = 0.7% 6h = 1.0% 7h = 1.2% 8h = 1.5% 9h = 2.0% Ah = 2.5% Bh = 3% Ch = 3.5% Dh = 4% Eh = 4.5% Fh = 5%
3	FIRST_CYCLE_FREQ_SEL	R/W	0h	First cycle frequency in open loop for align, double align and IPD startup options 0h = 0 Hz 1h = Defined by SLOW_FIRST_CYC_FREQ
2-0	THETA_ERROR_RAMP_RATE	R/W	0h	Ramp rate for reducing difference between estimated angle and open loop angle 0h = 0.01 deg/ms 1h = 0.05 deg/ms 2h = 0.1 deg/ms 3h = 0.15 deg/ms 4h = 0.2 deg / ms 5h = 0.5 deg/ms 6h = 1 deg/ms 7h = 2 deg/ms

7.7.1.5 CLOSED_LOOP1 Register (Offset = 88h) [Reset = 00000000h]

CLOSED_LOOP1 is shown in Table 7-20.

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Table 7-20 CLOSED_LOOP1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30	RESERVED	R/W	0h	Reserved
29-25	CL_ACC	R/W	0h	Closed loop acceleration Speed Mode ( Hz/s) Power Mode (W/s) Current Mode (A/s) Voltage Mode(0.1% modulation index per second) 0h = 0.5 1h = 1 2h = 2.5 3h = 5 4h = 7.5 5h = 10 6h = 20 7h = 40 8h = 60 9h = 80 Ah = 100 Bh = 200 Ch = 300 Dh = 400 Eh = 500 Fh = 600 10h = 700 11h = 800 12h = 900 13h = 1000 14h = 2000 15h = 4000 16h = 6000 17h = 8000 18h = 10000 19h = 20000 1Ah = 30000 1Bh = 40000 1Ch = 50000 1Dh = 60000 1Eh = 70000 1Fh = No limit
24	CL_DEC_CONFIG	R/W	0h	Closed loop deceleration configuration 0h = Closed loop deceleration defined by CL_DEC 1h = Closed loop deceleration defined by CL_ACC
23-19	CL_DEC	R/W	0h	Closed loop deceleration. Speed Mode ( Hz/s) Power Mode (W/s) Current Mode (A/s) Voltage Mode(0.1% modulation index per second) Note: This configuration bits are not used if AVS is enabled in speed mode or CL_DEC_CONFIG is set to '1' 0h = 0.5 1h = 1 2h = 2.5 3h = 5 4h = 7.5 5h = 10 6h = 20 7h = 40 8h = 60 9h = 80 Ah = 100 Bh = 200 Ch = 300 Dh = 400 Eh = 500 Fh = 600 10h = 700 11h = 800 12h = 900 13h = 1000 14h = 2000 15h = 4000 16h = 6000 17h = 8000 18h = 10000 19h = 20000 1Ah = 30000 1Bh = 40000 1Ch = 50000 1Dh = 60000 1Eh = 70000 1Fh = No limit
18-15	PWM_FREQ_OUT	R/W	0h	PWM output frequency 0h = 10 kHz 1h = 15 kHz 2h = 20 kHz 3h = 25 kHz 4h = 30 kHz 5h = 35 kHz 6h = 40 kHz 7h = 45 kHz 8h = 50 kHz 9h = 55 kHz Ah = 60 kHz Bh = 65 kHz Ch = 70 kHz Dh = 75 kHz Eh = Not Applicable Fh = Not Applicable
14	RESERVED	R/W	0h	Reserved
13-12	FG_SEL	R/W	0h	FG select 0h = Output FG in ISD, open loop and closed loop (HW config) 1h = Output FG in only closed loop 2h = Output FG in open loop for the first try. 3h = Not Defined
11-8	FG_DIV	R/W	0h	FG Division factor 0h = Divide by 1 (2-pole motor mechanical speed) 1h = Divide by 1 (2-pole motor mechanical speed) 2h = Divide by 2 (4-pole motor mechanical speed) 3h = Divide by 3 (6-pole motor mechanical speed) 4h = Divide by 4 (8-pole motor mechanical speed) ... Fh = Divide by 15 (30-pole motor mechanical speed)
7	FG_CONFIG	R/W	0h	FG output configuration 0h = FG active as long as motor is driven 1h = FG active till BEMF drops below BEMF threshold defined by FG_BEMF_THR
6-4	FG_BEMF_THR	R/W	0h	FG output BEMF threshold, calculated as voltage at SHx pin divided by voltage gain. Voltage gain = 20 V/V, BUS_VOLT = 60 Voltage gain = 10 V/V, BUS_VOLT = 30 Voltage gain = 5 V/V, BUS_VOLT = 15 0h = +/- 1mV 1h = +/- 2mV 2h = +/- 5mV 3h = +/- 10mV 4h = +/- 20mV 5h = +/- 30mV 6h = Not Applicable 7h = Not Applicable
3	AVS_EN	R/W	0h	AVS enable 0h = Disable 1h = Enable
2	DEADTIME_COMP_EN	R/W	0h	Deadtime compensation enable 0h = Disable 1h = Enable
1	RESERVED	R/W	0h	Reserved
0	LOW_SPEED_RECIRC_BRAKE_EN	R/W	0h	Motor stop option applied when MTR_STOP is recirculation Mode and motor is running in align or open loop 0h = Hi-z 1h = Low Side Brake

7.7.1.6 CLOSED_LOOP2 Register (Offset = 8Ah) [Reset = 00000000h]

CLOSED_LOOP2 is shown in Table 7-21.

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Table 7-21 CLOSED_LOOP2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-28	MTR_STOP	R/W	0h	Motor stop option 0h = Hi-z 1h = Recirculation Mode 2h = Low side braking 3h = Low side braking 4h = Active spin down 5h = Not Defined 6h = Not Defined 7h = Not Defined
27-24	MTR_STOP_BRK_TIME	R/W	0h	Brake time during motor stop 0h = 1 ms 1h = 1 ms 2h = 1 ms 3h = 1 ms 4h = 1 ms 5h = 5 ms 6h = 10 ms 7h = 50 ms 8h = 100 ms 9h = 250 ms Ah = 500 ms Bh = 1000 ms Ch = 2500 ms Dh = 5000 ms Eh = 10000 ms Fh = 15000 ms
23-20	ACT_SPIN_THR	R/W	0h	Speed threshold for active spin down (% of MAX_SPEED) 0h = 100 % 1h = 90 % 2h = 80 % 3h = 70 % 4h = 60% 5h = 50 % 6h = 45 % 7h = 40 % 8h = 35 % 9h = 30 % Ah = 25 % Bh = 20 % Ch = 15 % Dh = 10 % Eh = 5 % Fh = 2.5 %
19-16	BRAKE_SPEED_THRESHOLD	R/W	0h	Speed threshold below which brake is applied for BRAKE pin and Motor stop options (Low side Braking) (% of MAX_SPEED) 0h = 100 % 1h = 90 % 2h = 80 % 3h = 70 % 4h = 60% 5h = 50 % 6h = 45 % 7h = 40 % 8h = 35 % 9h = 30 % Ah = 25 % Bh = 20 % Ch = 15 % Dh = 10 % Eh = 5 % Fh = 2.5 %
15-8	MOTOR_RES	R/W	0h	8-bit values for motor phase resistance
7-0	MOTOR_IND	R/W	0h	8-bit values for motor phase inductance

7.7.1.7 CLOSED_LOOP3 Register (Offset = 8Ch) [Reset = 00000000h]

CLOSED_LOOP3 is shown in Table 7-22.

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Table 7-22 CLOSED_LOOP3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-23	MOTOR_BEMF_CONST	R/W	0h	8-bit values for motor BEMF Constant
22-13	CURR_LOOP_KP	R/W	0h	10-bit Kp value for Iq and Id PI loop. CURR_LOOP_KP is divided in 2 sections. SCALE(9:8) and VALUE(7:0). Kp = VALUE / 10^SCALE Set to 0 for auto calculation of current Kp and Ki
12-3	CURR_LOOP_KI	R/W	0h	10-bit Ki value for Iq and Id PI loop. CURR_LOOP_KI is divided in 2 sections. SCALE(9:8) and VALUE(7:0). Ki = 1000 × VALUE / 10^SCALE Set to 0 for auto calculation of current Kp and Ki
2-0	SPD_LOOP_KP	R/W	0h	3 MSB bits for speed loop Kp. SPD_LOOP_KP is divided in 2 sections SCALE(9:8) and VALUE(7:0). Kp = 0.01 × VALUE / 10^SCALE.

7.7.1.8 CLOSED_LOOP4 Register (Offset = 8Eh) [Reset = 00000000h]

CLOSED_LOOP4 is shown in Table 7-23.

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Table 7-23 CLOSED_LOOP4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-24	SPD_LOOP_KP	R/W	0h	7 LSB bits for speed loop Kp. SPD_LOOP_KP is divided in 2 sections SCALE(10:9) and VALUE(8:0). Kp = 0.01 × VALUE / 10^SCALE.
23-14	SPD_LOOP_KI	R/W	0h	10 bit value for speed loop Ki. SPD_LOOP_KI is divided in 2 sections SCALE(9:8) and VALUE(7:0). Ki = 0.1 × VALUE / 10^SCALE.
13-0	MAX_SPEED	R/W	0h	14-bit value for setting maximum value of Speed in electrical Hz. 0 - 9600d = MAX_SPEED/6 9601d - 16383d = (MAX_SPEED/4 - 800) For example, if MAX_SPEED is 0x5DC(1500d), then maximum motor speed (Hz) is 1500/6 is equal to 250Hz If MAX_SPEED is 0x2710(10000d), then maximum motor speed (Hz) is (10000/4) - 800 is equal to 1700 Hz

7.7.1.9 REF_PROFILES1 Register (Offset = 94h) [Reset = 00000000h]

REF_PROFILES1 is shown in Table 7-24.

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Table 7-24 REF_PROFILES1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-29	REF_PROFILE_CONFIG	R/W	0h	Configuration for Reference profiles 0h = Reference Mode 1h = Linear Mode 2h = Staircase Mode 3h = Forward Reverse Mode
28-21	DUTY_ON1	R/W	0h	Duty_ON1 Configuration Turn On Duty Cycle (%) = {(DUTY_ON1/255) × 100}
20-13	DUTY_OFF1	R/W	0h	Duty_OFF1 Configuration Turn Off Duty Cycle (%) = {(DUTY_OFF1/255) × 100}
12-5	DUTY_CLAMP1	R/W	0h	Duty_CLAMP1 Configuration Duty Cycle for clamping (%) = {(DUTY_CLAMP1/255) ×100}
4-0	DUTY_A	R/W	0h	5 MSB bits for Duty Cycle A

7.7.1.10 REF_PROFILES2 Register (Offset = 96h) [Reset = 00000000h]

REF_PROFILES2 is shown in Table 7-25.

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Table 7-25 REF_PROFILES2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-28	DUTY_A	R/W	0h	3 LSB bits for Duty Cycle A Configuration Duty Cycle A (%) = {(DUTY_A/255) × 100}
27-20	DUTY_B	R/W	0h	Duty_B Configuration Duty Cycle B (%) = {(DUTY_B/255) × 100}
19-12	DUTY_C	R/W	0h	Duty_C Configuration Duty Cycle C (%) = {(DUTY_C/255) × 100}
11-4	DUTY_D	R/W	0h	Duty_D Configuration Duty Cycle D (%) = {(DUTY_D/255) × 100}
3-0	DUTY_E	R/W	0h	4 MSB bits for Duty Cycle E

7.7.1.11 REF_PROFILES3 Register (Offset = 98h) [Reset = 00000000h]

REF_PROFILES3 is shown in Table 7-26.

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Table 7-26 REF_PROFILES3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-27	DUTY_E	R/W	0h	4 LSB bits for Duty Cycle E Configuration Duty Cycle E (%) = {(DUTY_E/255) × 100}
26-19	DUTY_ON2	R/W	0h	Duty_ON2 Configuration Turn On Duty Cycle (%) = {(DUTY_ON2/255) × 100}
18-11	DUTY_OFF2	R/W	0h	Duty_OFF2 Configuration Turn Off Duty Cycle (%) = {(DUTY_OFF2/255) × 100}
10-3	DUTY_CLAMP2	R/W	0h	Duty_CLAMP2 Configuration Duty Cycle for clamping (%) = {(DUTY_CLAMP2/255) × 100}
2-1	DUTY_HYS	R/W	0h	Duty hysteresis 0h = 0% 1h = 0.8% 2h = 2% 3h = 4%
0	RESERVED	R/W	0h	Reserved

7.7.1.12 REF_PROFILES4 Register (Offset = 9Ah) [Reset = 00000000h]

REF_PROFILES4 is shown in Table 7-27.

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Table 7-27 REF_PROFILES4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-23	REF_OFF1	R/W	0h	Turn off ref Configuration Turn off reference (% of Maximum Reference) = {(REF_OFF1/255) × 100}
22-15	REF_CLAMP1	R/W	0h	Ref Clamp1 Configuration Clamp Ref (% of Maximum Reference) = {(REF_CLAMP1/255) × 100}
14-7	REF_A	R/W	0h	Ref A configuration Ref A (% of Maximum Reference) = {(REF_A/255) × 100}
6-0	REF_B	R/W	0h	7 MSB of REF_B configuration

7.7.1.13 REF_PROFILES5 Register (Offset = 9Ch) [Reset = 00000000h]

REF_PROFILES5 is shown in Table 7-28.

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Table 7-28 REF_PROFILES5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30	REF_B	R/W	0h	1 LSB of REF_B configuration Ref B(% of Maximum Reference) = {(REF_B/255) × 100}
29-22	REF_C	R/W	0h	Ref C configuration Ref C (% of Maximum Reference) = {(REF_C/255) × 100}
21-14	REF_D	R/W	0h	Ref D configuration Ref D (% of Maximum Reference) = {(REF_D/255) × 100}
13-6	REF_E	R/W	0h	Ref E Configuration Ref E(% of Maximum Reference) = {(REF_E/255)*100}
5-0	RESERVED	R/W	0h	Reserved

7.7.1.14 REF_PROFILES6 Register (Offset = 9Eh) [Reset = 00000000h]

REF_PROFILES6 is shown in Table 7-29.

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Table 7-29 REF_PROFILES6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-23	REF_OFF2	R/W	0h	Turn off Ref Configuration Turn off Ref (% of Maximum Reference)) = {(REF_OFF2/255) × 100}
22-15	REF_CLAMP2	R/W	0h	Clamp Ref Configuration Clamp Ref (% of Maximum Reference) = {(REF_CLAMP2/255) ×100}
14-0	RESERVED	R/W	0h	Reserved