SLAS508K Data sheet

SLAS508K April 2006 – May 2020 MSP430FG4616 , MSP430FG4617 , MSP430FG4618 , MSP430FG4619

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

ZQW|113
- MPBG674
ZCA|113
- MPBGAJ3A
PZ|100
- MTQF013A

Thermal pad, mechanical data (Package|Pins)

PZ|100
- QFND428

Orderable Information

6.9.17 Peripheral File Map

Table 6-9 lists the registers and addresses for peripherals with word access. Table 6-10 lists the registers and addresses for peripherals with byte access.

Table 6-9 Peripherals With Word Access

MODULE	REGISTER NAME	ACRONYM	ADDRESS
Watchdog+	Watchdog timer control	WDTCTL	0120h
Timer_B7	Capture/compare register 6 Capture/compare register 5 Capture/compare register 4 Capture/compare register 3 Capture/compare register 2 Capture/compare register 1 Capture/compare register 0 Timer_B register Capture/compare control 6 Capture/compare control 5 Capture/compare control 4 Capture/compare control 3 Capture/compare control 2 Capture/compare control 1 Capture/compare control 0 Timer_B control Timer_B interrupt vector	TBCCR6 TBCCR5 TBCCR4 TBCCR3 TBCCR2 TBCCR1 TBCCR0 TBR TBCCTL6 TBCCTL5 TBCCTL4 TBCCTL3 TBCCTL2 TBCCTL1 TBCCTL0 TBCTL TBIV	019Eh 019Ch 019Ah 0198h 0196h 0194h 0192h 0190h 018Eh 018Ch 018Ah 0188h 0186h 0184h 0182h 0180h 011Eh
Timer_A3	Capture/compare register 2 Capture/compare register 1 Capture/compare register 0 Timer_A register Capture/compare control 2 Capture/compare control 1 Capture/compare control 0 Timer_A control Timer_A interrupt vector	TACCR2 TACCR1 TACCR0 TAR TACCTL2 TACCTL1 TACCTL0 TACTL TAIV	0176h 0174h 0172h 0170h 0166h 0164h 0162h 0160h 012Eh
Hardware Multiplier	Sum extend Result high word Result low word Second operand Multiply signed + accumulate/operand1 Multiply + accumulate/operand1 Multiply signed/operand1 Multiply unsigned/operand1	SUMEXT RESHI RESLO OP2 MACS MAC MPYS MPY	013Eh 013Ch 013Ah 0138h 0136h 0134h 0132h 0130h
Flash (FG devices only)	Flash control 3 Flash control 2 Flash control 1	FCTL3 FCTL2 FCTL1	012Ch 012Ah 0128h
DMA	DMA module control 0 DMA module control 1 DMA interrupt vector	DMACTL0 DMACTL1 DMAIV	0122h 0124h 0126h
DMA Channel 0	DMA channel 0 control DMA channel 0 source address DMA channel 0 destination address DMA channel 0 transfer size	DMA0CTL DMA0SA DMA0DA DMA0SZ	01D0h 01D2h 01D6h 01DAh
DMA Channel 1	DMA channel 1 control DMA channel 1 source address DMA channel 1 destination address DMA channel 1 transfer size	DMA1CTL DMA1SA DMA1DA DMA1SZ	01DCh 01DEh 01E2h 01E6h
DMA Channel 2	DMA channel 2 control DMA channel 2 source address DMA channel 2 destination address DMA channel 2 transfer size	DMA2CTL DMA2SA DMA2DA DMA2SZ	01E8h 01EAh 01EEh 01F2h
ADC12 See also Table 6-10	Conversion memory 15 Conversion memory 14 Conversion memory 13 Conversion memory 12 Conversion memory 11 Conversion memory 10 Conversion memory 9 Conversion memory 8 Conversion memory 7 Conversion memory 6 Conversion memory 5 Conversion memory 4 Conversion memory 3 Conversion memory 2 Conversion memory 1 Conversion memory 0 Interrupt-vector-word register Inerrupt-enable register Inerrupt-flag register Control register 1 Control register 0	ADC12MEM15 ADC12MEM14 ADC12MEM13 ADC12MEM12 ADC12MEM11 ADC12MEM10 ADC12MEM9 ADC12MEM8 ADC12MEM7 ADC12MEM6 ADC12MEM5 ADC12MEM4 ADC12MEM3 ADC12MEM2 ADC12MEM1 ADC12MEM0 ADC12IV ADC12IE ADC12IFG ADC12CTL1 ADC12CTL0	015Eh 015Ch 015Ah 0158h 0156h 0154h 0152h 0150h 014Eh 014Ch 014Ah 0148h 0146h 0144h 0142h 0140h 01A8h 01A6h 01A4h 01A2h 01A0h
DAC12	DAC12_1 data DAC12_1 control DAC12_0 data DAC12_0 control	DAC12_1DAT DAC12_1CTL DAC12_0DAT DAC12_0CTL	01CAh 01C2h 01C8h 01C0h
Port PA	Port PA selection Port PA direction Port PA output Port PA input	PASEL PADIR PAOUT PAIN	03Eh 03Ch 03Ah 038h
Port PB	Port PB selection Port PB direction Port PB output Port PB input	PBSEL PBDIR PBOUT PBIN	00Eh 00Ch 00Ah 008h

Table 6-10 Peripherals With Byte Access

MODULE	REGISTER NAME	ACRONYM	ADDRESS
OA2	Operational Amplifier 2 control register 1 Operational Amplifier 2 control register 0	OA2CTL1 OA2CTL0	0C5h 0C4h
OA1	Operational Amplifier 1 control register 1 Operational Amplifier 1 control register 0	OA1CTL1 OA1CTL0	0C3h 0C2h
OA0	Operational Amplifier 0 control register 1 Operational Amplifier 0 control register 0	OA0CTL1 OA0CTL0	0C1h 0C0h
LCD_A	LCD Voltage Control 1 LCD Voltage Control 0 LCD Voltage Port Control 1 LCD Voltage Port Control 0 LCD memory 20 : LCD memory 16 LCD memory 15 : LCD memory 1 LCD control and mode	LCDAVCTL1 LCDAVCTL0 LCDAPCTL1 LCDAPCTL0 LCDM20 : LCDM16 LCDM15 : LCDM1 LCDCTL	0AFh 0AEh 0ADh 0ACh 0A4h : 0A0h 09Fh : 091h 090h
ADC12 (Memory control registers require byte access)	ADC memory-control register 15 ADC memory-control register 14 ADC memory-control register 13 ADC memory-control register 12 ADC memory-control register 11 ADC memory-control register 10 ADC memory-control register 9 ADC memory-control register 8 ADC memory-control register 7 ADC memory-control register 6 ADC memory-control register 5 ADC memory-control register 4 ADC memory-control register 3 ADC memory-control register 2 ADC memory-control register 1 ADC memory-control register 0	ADC12MCTL15 ADC12MCTL14 ADC12MCTL13 ADC12MCTL12 ADC12MCTL11 ADC12MCTL10 ADC12MCTL9 ADC12MCTL8 ADC12MCTL7 ADC12MCTL6 ADC12MCTL5 ADC12MCTL4 ADC12MCTL3 ADC12MCTL2 ADC12MCTL1 ADC12MCTL0	08Fh 08Eh 08Dh 08Ch 08Bh 08Ah 089h 088h 087h 086h 085h 084h 083h 082h 081h 080h
USART1	Transmit buffer Receive buffer Baud rate Baud rate Modulation control Receive control Transmit control USART control	U1TXBUF U1RXBUF U1BR1 U1BR0 U1MCTL U1RCTL U1TCTL U1CTL	07Fh 07Eh 07Dh 07Ch 07Bh 07Ah 079h 078h
USCI	USCI I2C Slave Address USCI I2C Own Address USCI Synchronous Transmit Buffer USCI Synchronous Receive Buffer USCI Synchronous Status USCI I2C Interrupt Enable USCI Synchronous Bit Rate 1 USCI Synchronous Bit Rate 0 USCI Synchronous Control 1 USCI Synchronous Control 0 USCI Transmit Buffer USCI Receive Buffer USCI Status USCI Modulation Control USCI Baud Rate 1 USCI Baud Rate 0 USCI Control 1 USCI Control 0 USCI IrDA Receive Control USCI IrDA Transmit Control USCI LIN Control	UCBI2CSA UCBI2COA UCBTXBUF UCBRXBUF UCBSTAT UCBI2CIE UCBBR1 UCBBR0 UCBCTL1 UCBCTL0 UCATXBUF UCARXBUF UCASTAT UCAMCTL UCABR1 UCABR0 UCACTL1 UCACTL0 UCAIRRCTL UCAIRTCTL UCAABCTL	011Ah 0118h 06Fh 06Eh 06Dh 06Ch 06Bh 06Ah 069h 068h 067h 066h 065h 064h 063h 062h 061h 060h 05Fh 05Eh 05Dh
Comparator_A	Comparator_A port disable Comparator_A control 2 Comparator_A control 1	CAPD CACTL2 CACTL1	05Bh 05Ah 059h
BrownOUT, SVS	SVS control register (Reset by brownout signal)	SVSCTL	056h
FLL+Clock	FLL+ Control 1 FLL+ Control 0 System clock frequency control System clock frequency integrator System clock frequency integrator	FLL_CTL1 FLL_CTL0 SCFQCTL SCFI1 SCFI0	054h 053h 052h 051h 050h
RTC (Basic Timer 1)	Real Time Clock Year High Byte Real Time Clock Year Low Byte Real Time Clock Month Real Time Clock Day of Month Basic Timer1 Counter 2 Basic Timer1 Counter 1 Real Time Counter 4 (Real Time Clock Day of Week) Real Time Counter 3 (Real Time Clock Hour) Real Time Counter 2 (Real Time Clock Minute) Real Time Counter 1 (Real Time Clock Second) Real Time Clock Control Basic Timer1 Control	RTCYEARH RTCYEARL RTCMON RTCDAY BTCNT2 BTCNT1 RTCNT4 (RTCDOW) RTCNT3 (RTCHOUR) RTCNT2 (RTCMIN) RTCNT1 (RTCSEC) RTCCTL BTCTL	04Fh 04Eh 04Dh 04Ch 047h 046h 045h 044h 043h 042h 041h 040h
Port P10	Port P10 selection Port P10 direction Port P10 output Port P10 input	P10SEL P10DIR P10OUT P10IN	00Fh 00Dh 00Bh 009h
Port P9	Port P9 selection Port P9 direction Port P9 output Port P9 input	P9SEL P9DIR P9OUT P9IN	00Eh 00Ch 00Ah 008h
Port P8	Port P8 selection Port P8 direction Port P8 output Port P8 input	P8SEL P8DIR P8OUT P8IN	03Fh 03Dh 03Bh 039h
Port P7	Port P7 selection Port P7 direction Port P7 output Port P7 input	P7SEL P7DIR P7OUT P7IN	03Eh 03Ch 03Ah 038h
Port P6	Port P6 selection Port P6 direction Port P6 output Port P6 input	P6SEL P6DIR P6OUT P6IN	037h 036h 035h 034h
Port P5	Port P5 selection Port P5 direction Port P5 output Port P5 input	P5SEL P5DIR P5OUT P5IN	033h 032h 031h 030h
Port P4	Port P4 selection Port P4 direction Port P4 output Port P4 input	P4SEL P4DIR P4OUT P4IN	01Fh 01Eh 01Dh 01Ch
Port P3	Port P3 selection Port P3 direction Port P3 output Port P3 input	P3SEL P3DIR P3OUT P3IN	01Bh 01Ah 019h 018h
Port P2	Port P2 selection Port P2 interrupt enable Port P2 interrupt-edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input	P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN	02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h
Port P1	Port P1 selection Port P1 interrupt enable Port P1 interrupt-edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input	P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN	026h 025h 024h 023h 022h 021h 020h
Special functions	SFR module enable 2 SFR module enable 1 SFR interrupt flag 2 SFR interrupt flag 1 SFR interrupt enable 2 SFR interrupt enable 1	ME2 ME1 IFG2 IFG1 IE2 IE1	005h 004h 003h 002h 001h 000h