SLASF11D February   2023  – October 2025 MSPM0G1105 , MSPM0G1106 , MSPM0G1107

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Ramp
      1. 7.6.1 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
        1. 7.9.1.1 SYSOSC Typical Frequency Accuracy
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
    13. 7.13 Typical Connection Diagram
    14. 7.14 Temperature Sensor
    15. 7.15 VREF
      1. 7.15.1 Voltage Characteristics
      2. 7.15.2 Electrical Characteristics
    16. 7.16 GPAMP
      1. 7.16.1 Electrical Characteristics
      2. 7.16.2 Switching Characteristics
    17. 7.17 I2C
      1. 7.17.1 I2C Timing Diagram
      2. 7.17.2 I2C Characteristics
      3. 7.17.3 I2C Filter
    18. 7.18 SPI
      1. 7.18.1 SPI
      2. 7.18.2 SPI Timing Diagram
    19. 7.19 UART
    20. 7.20 TIMx
    21. 7.21 Emulation and Debug
      1. 7.21.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0G110x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 GPAMP
    16. 8.16 CRC
    17. 8.17 UART
    18. 8.18 I2C
    19. 8.19 SPI
    20. 8.20 WWDT
    21. 8.21 RTC
    22. 8.22 Timers (TIMx)
    23. 8.23 Device Analog Connections
    24. 8.24 Input/Output Diagrams
    25. 8.25 Serial Wire Debug Interface
    26. 8.26 Bootstrap Loader (BSL)
    27. 8.27 Device Factory Constants
    28. 8.28 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGZ|48
  • PT|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3 Signal Descriptions

Many MSPM0 signals are made available on multiple device pins. The following list describes the column headers:

  1. SIGNAL NAME: The name of the signal which can be connected to one of the specified pins.
  2. PIN TYPE: The signal direction and signal type:
    • I = Input
    • O = Output
    • IO = Input, output, or simultaneous input and output
    • ID = Input with open-drain behavior
    • OD = Output with open-drain behavior
    • IOD = Input, output, or simultaneous input and output with open-drain behavior
    • A = Analog
    • PWR = Power function
  3. DESCRIPTION: A description of the signal.
  4. PIN: Associated pin number.

For additional information on the pin multiplexing scheme, refer to the IOMUX chapter of the MSPM0 G-Series 80MHz Microcontrollers Technical Reference Manual.

Note: The IOMUX only supports connecting one IOMUX-managed digital function to the pin at the same time. However, non-IOMUX managed signals (such as analog inputs and WAKE inputs) can be enabled on a pin at the same time that an IOMUX managed digital function is enabled on the pin. In this case, the designer must verify that no contention exists between the functions enabled on each pin.
Table 6-3 Signal Descriptions
FUNCTION SIGNAL NAME PIN NO. (1) PIN TYPE (2) DESCRIPTION
64 PM 48 PT, RGZ 32 RHB 28 DGS28 24 VQFN 28 DSBGA
ADC A0_0 31 47 31 2 – C3 I ADC0 analog input 0
A0_1 30 46 30 1 22 B3 I ADC0 analog input 1
A0_2 26 45 29 28 21 E2 I ADC0 analog input 2
A0_3 25 44 28 27 20 A3 I ADC0 analog input 3
A0_4 27 – – – – – I ADC0 analog input 4
A0_5 23 42 – – – – I ADC0 analog input 5
A0_6 19 41 – – – – I ADC0 analog input 6
A0_7 18 40 26 25 18 C2 I ADC0 analog input 7
A0_12 7 29 18 17 – - I ADC0 analog input 12
A1_0 8 30 19 18 11 F1 I ADC1 analog input 0
A1_1 9 31 20 19 12 E1 I ADC1 analog input 1
A1_2 10 32 21 20 13 - I ADC1 analog input 2
A1_3 11 33 22 21 14 B1 I ADC1 analog input 3
A1_4 14 36 – – – – I ADC1 analog input 4
A1_5 15 37 – – – – I ADC1 analog input 5
A1_6 16 38 – – – A1 I ADC1 analog input 6
A1_7 17 39 25 24 17 D2 I ADC1 analog input 7
BSL BSL_invoke 11 33 22 21 14 B1 I Input pin used to invoke bootloader
BSL (I2C) BSLSCL 34 2 2 5 1 E3 I/O Default I2C BSL clock
BSLSDA 33 1 1 4 24 D3 I/O Default I2C BSL data
BSL (UART) BSLRX 57 19 15 16 10 G2 I Default UART BSL receive
BSLTX 56 18 14 15 9 G1 O Default UART BSL transmit
Clock CLK_OUT 7
18
39
49
55
56
63		 5
13
17
18
29
40		 11
13
14
18
26		 14
15
17
25		 8
9
18		 F2
G1

C2		 O Configurable clock output
HFCLK_IN 46 12 10 13 – G3 I Digital high-frequency clock input
HFXIN 45 11 9 12 – F3 I Input for high-frequency crystal oscillator HFXT
HFXOUT 46 12 10 13 – G3 O Output for high-frequency crystal oscillator HFXT
LFCLK_IN 44 10 8 11 7 G4 I Digital low-frequency clock input
LFXIN 43 9 7 10 – F4 I Input for low-frequency crystal oscillator LFXT
LFXOUT 44 10 8 11 7 G4 O Output of low-frequency crystal oscillator LFXT
ROSC 42 8 6 9 5 E4 I External resistor used for improving oscillator accuracy
Debug SWCLK 13 35 24 23 16 D1 I Serial wire debug input clock
SWDIO 12 34 23 22 15 C1 I/O Serial wire debug data input/output
FCC FCC_IN 5
9
33
45		 1
11
27
31		 1
9
16
20		 4
12
19		 12
24		 D3
F3
E1		 I Frequency clock counter input
General-Purpose Amplifier GPAMP_IN+ 30 46 30 1 22 B3 I GPAMP noninverting terminal input
GPAMP_IN- 11 33 22 21 14 B1 I GPAMP inverting terminal input
GPAMP_OUT 18 40 26 25 18 C2 O GPAMP output
GPIO PA0 33 1 1 4 24 D3 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA1 34 2 2 5 1 E3 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA2 42 8 6 9 5 E4 I/O General-purpose digital I/O
PA3 43 9 7 10 6 F4 I/O General-purpose digital I/O
PA4 44 10 8 11 7 G4 I/O General-purpose digital I/O
PA5 45 11 9 12 – F3 I/O General-purpose digital I/O
PA6 46 12 10 13 – G3 I/O General-purpose digital I/O
PA7 49 13 11 – – – I/O General-purpose digital I/O
PA8 54 16 12 – – – I/O General-purpose digital I/O
PA9 55 17 13 14 8 F2 I/O General-purpose digital I/O
PA10 56 18 14 15 9 G1 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA11 57 19 15 16 10 G2 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA12 5 27 16 – – – I/O General-purpose digital I/O
PA13 6 28 17 – – – I/O General-purpose digital I/O
PA14 7 29 18 17 – – I/O General-purpose digital I/O
PA15 8 30 19 18 11 F1 I/O General-purpose digital I/O
PA16 9 31 20 19 12 E1 I/O General-purpose digital I/O
PA17 10 32 21 20 13 – I/O General-purpose digital I/O with wake up from SHUTDOWN
PA18 11 33 22 21 14 B1 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA19 12 34 23 22 15 C1 I/O General-purpose digital I/O
PA20 13 35 24 23 16 D1 I/O General-purpose digital I/O
PA21 17 39 25 24 17 D2 I/O General-purpose digital I/O
PA22 18 40 26 25 18 C2 I/O General-purpose digital I/O
PA23 24 43 27 26 19 A2 I/O General-purpose digital I/O
PA24 25 44 28 27 20 A3 I/O General-purpose digital I/O
PA25 26 45 29 28 21 E2 I/O General-purpose digital I/O
PA26 30 46 30 1 22 B3 I/O General-purpose digital I/O
PA27 31 47 31 2 – C3 I/O General-purpose digital I/O
PA28 35 3 – – – – I/O General-purpose digital I/O with wake up from SHUTDOWN
PA29 36 – – – – – I/O General-purpose digital I/O
PA30 37 – – – – – I/O General-purpose digital I/O
PA31 39 5 – – – – I/O General-purpose digital I/O with wake up from SHUTDOWN
GPIO PB0 47 – – – – – I/O General-purpose digital I/O
PB1 48 – – – – – I/O General-purpose digital I/O
PB2 50 14 – – – – I/O General-purpose digital I/O
PB3 51 15 – – – – I/O General-purpose digital I/O
PB4 52 – – – – – I/O General-purpose digital I/O
PB5 53 – – – – – I/O General-purpose digital I/O
PB6 58 20 – – – – I/O General-purpose digital I/O
PB7 59 21 – – – – I/O General-purpose digital I/O
PB8 60 22 – – – – I/O General-purpose digital I/O
PB9 61 23 – – – – I/O General-purpose digital I/O
PB10 62 – – – – – I/O General-purpose digital I/O
PB11 63 – – – – – I/O General-purpose digital I/O
PB12 64 – – – – – I/O General-purpose digital I/O
PB13 1 – – – – – I/O General-purpose digital I/O
PB14 2 24 – – – – I/O General-purpose digital I/O
PB15 3 25 – – – – I/O General-purpose digital I/O
PB16 4 26 – – – – I/O General-purpose digital I/O
PB17 14 36 – – – – I/O General-purpose digital I/O
PB18 15 37 – – – – I/O General-purpose digital I/O
PB19 16 38 – – – A1 I/O General-purpose digital I/O
PB20 19 41 – – – – I/O General-purpose digital I/O
PB21 20 – – – – – I/O General-purpose digital I/O
PB22 21 – – – – – I/O General-purpose digital I/O
PB23 22 – – – – B2 I/O General-purpose digital I/O
PB24 23 42 – – – – I/O General-purpose digital I/O
PB25 27 – – – – – I/O General-purpose digital I/O
PB26 28 – – – – – I/O General-purpose digital I/O
PB27 29 – – – – – I/O General-purpose digital I/O
I2C I2C0_SCL 34
39
57		 2
5
19		 2
15		 5
16		 1
10		 E3
G2		 I/O I2C0 serial clock
I2C0_SDA 33
35
56		 1
3
18		 1
14		 4
15		 9
24		 D3
G1		 I/O I2C0 serial data
I2C1_SCL 8
10
36
44
50
57		 10
14
19
30
32		 8
15
19
21		 11
16
18
20		 7
10
11
13		 G4
G2
F1		 I/O I2C1 serial clock
I2C1_SDA 9
11
37
43
51
56		 9
15
18
31
33		 7
14
20
22		 10
15
19
21		 6
9
12
14		 F4
G1
E1
B1		 I/O I2C1 serial data
Power VSS 41 7 5 8 4 D4 P Ground supply
VDD 40 6 4 7 3 C4 P Power supply
VCORE 32 48 32 3 23 A4 P Regulated core power supply output
QFN Pad – Pad Pad – Pad – P QFN package exposed thermal pad. TI recommends connection to VSS.
RTC RTC_OUT 31
55		 17
47		 13
31		 2
14		 8 C3
F2		 O RTC clock output
SPI SPI0_CS0 27
42
54		 8
16		 6
12		 9 5 E4 I/O SPI0 chip-select 0
SPI0_CS1 23
28
43
58		 9
20
42		 7 10 6 F4 I/O SPI0 chip-select 1
SPI0_CS2 19
25
59		 21
41
44		 28 27 20 A3 I/O SPI0 chip-select 2
SPI0_CS3 2
23
24		 24
42
43		 27 26 19 A2 I/O SPI0 chip-select 3
SPI0_SCK 5
15
46
57		 12
19
27
37		 10
15
16		 13
16		 10 G3
G2		 I/O SPI0 clock signal input – SPI peripheral mode
Clock signal output – SPI controller mode
SPI0_POCI 6
16
44
56		 10
18
28
38		 8
14
17		 11
15		 7
9		 G4
G1
A1		 I/O SPI0 controller in/peripheral out
SPI0_PICO 7
14
45
55		 11
17
29
36		 9
13
18		 12
14
17		 8 F3
F2		 I/O SPI0 controller out/peripheral in
SPI1_CS0 19
30
42
58		 8
20
41
46		 6
30		 1
9		 5
22		 B3
E4		 I/O SPI1 chip-select 0
SPI1_CS1 14
29
31		 36
47		 31 2 – C3 I/O SPI1 chip-select 1
SPI1_CS2 8
15
47		 30
37		 19 18 11 F1 I/O SPI1 chip-select 2
SPI1_CS3 2
26
48		 24
45		 29 28 21 E2 I/O SPI1 chip-select 3
SPI1_SCK 4
10
22
61		 23
26
32		 21 20 13 B2 I/O SPI1 clock signal input – SPI peripheral mode
Clock signal output – SPI controller mode
SPI1_POCI 2
9
20
59		 21
24
31		 20 19 12 E1 I/O SPI1 controller in/peripheral out
SPI1_PICO 3
11
21
60		 22
25
33		 22 21 14 B1 I/O SPI1 controller out/peripheral in
System NRST 38 4 3 6 2 B4 I Reset input active low
Timer TIMG0_C0 5
24
45
62		 11
27
43		 9
16
27		 12
26		 19 F3
A2		 I/O General purpose timer 0 CCR0 capture input or compare output
TIMG0_C1 6
25
46
63		 12
28
44		 10
17
28		 13
27		 20 G3
A3		 I/O General purpose timer 0 CCR1 capture input or compare output
TIMG6_C0 17
28
36
45
50
58
62		 11
14
20
39		 9
25		 12
24		 17 F3
D2		 I/O General purpose timer 6 CCR0 capture input or compare output
TIMG6_C1 18
29
37
46
51
59
63		 12
15
21
40		 10
26		 13
25		 18 G3
C2		 I/O General purpose timer 6 CCR1 capture input or compare output
TIMG7_C0 3
10
24
30
35
43		 3
9
25
32
43
46		 7
21
27
30		 1
10
20
26		 6
13
19
22		 B3
F4
A2		 I/O General purpose timer 7 CCR1 capture input or compare output
TIMG7_C1 4
11
16
25
31
39
42
44
49		 5
8
10
13
26
33
38
44
47		 6
8
11
22
28
31		 2
9
11
21
27		 5
7
14
20		 C3
E4
G4
B1
A3
A1		 I/O General purpose timer 7 CCR1 capture input or compare output
TIMG8_C0 3
17
20
24
30
34
36
43
45
49
58
62		 2
9
11
13
20
25
39
43
46		 2
7
9
11
25
27
30		 1
5
10
12
24
26		 1
6
17
19
22		 B3
E3
F4
F3
D2
A2		 I/O General purpose timer 8 CCR0 capture input or compare output
Timer (continued) TIMG8_C1 4
16
18
21
31
33
37
42
44
46
59
63		 1
8
10
12
21
26
38
40
47		 1
6
8
10
26
31		 2
4
9
11
13
25		 5
7
18
24		 C3
D3
E4
G4
G3
C2		 I/O General purpose timer 8 CCR1 capture input or compare output
TIMG8_IDX 2
8
34
49		 2
13
24
30		 2
11
19		 5
18		 1
11		 E3
F1		 I General purpose timer 8 quadrature encoder index pulse input
TIMG12_C0 1
7
19
56		 18
29
41		 14
18		 15
17		 9 G1 I/O 32-bit general purpose timer 0 CCR0 capture input or compare output
TIMG12_C1 2
23
26
39		 5
24
42
45		 29 28 21 E2 I/O 32-bit general purpose timer 0 CCR1 capture input or compare output
TIMA0_C0 2
17
33
54
60		 1
16
22
24
39		 1
12
25		 4
24		 17
24		 D3
D2		 I/O Advanced control timer 0 CCR0 capture input/compare output
TIMA0_C0N 18
55
61		 17
23
40		 13
26		 14
25		 8
18		 F2
C2		 I/O Advanced control timer 0 CCR0 compare output (inverting)
TIMA0_C1 18
34
43
49
55
61
64		 2
9
13
17
23
41		 2
7
11
13
26		 5
10
14
25		 1
6
8
18		 E3
F4
F2
C2		 I/O Advanced control timer 0 CCR1 capture input or compare output
TIMA0_C1N 1
19
23
26
44
55		 10
17
42
45		 8
13
29		 11
14
28		 7
21		 G4
E2		 I/O Advanced control timer 0 CCR1 compare output (inverting)
Timer (continued) TIMA0_C2 8
14
19
43
47
49
52
56
64		 9
13
18
30
36
41		 7
11
14
19		 10
15
18		 6
9
11		 F4
G1
F1		 I/O Advanced control timer 0 CCR2 capture input or compare output
TIMA0_C2N 9
15
46
48
53
57		 12
19
31
37		 10
15
20		 13
16
19		 10
12		 G3
G2
E1		 I/O Advanced control timer 0 CCR2 compare output (inverting)
TIMA0_C3 1
5
10
23
24
26
28
35
44
50		 3
10
14
27
32
42
43
45		 8
16
21
27
29		 11
20
26
28		 7
13
19
21		 G4
A2
E2		 I/O Advanced control timer 0 CCR3 capture input or compare output
TIMA0_C3N 6
11
25
29
39
51		 5
15
28
33
44		 17
22
28		 21
27		 14
20		 B1
A3		 I/O Advanced control timer 0 CCR3 compare output (inverting)
TIMA1_C0 8
10
14
28
35
47
50
52
56		 3
14
18
30
32
36		 14
19
21		 15
18
20		 9
11
13		 G1
F1		 I/O Advanced control timer 1 CCR0 capture input or compare output
TIMA1_C0N 8
23
52
54
58		 16
20
30
42		 12
19		 18 11 F1 I/O Advanced control timer 0 CCR3 compare output (inverting)
TIMA1_C1 9
11
15
25
29
39
48
51
53
57		 5
15
19
31
33
37
44		 15
20
22
28		 16
19
21
27		 10
12
14
20		 G2
E1
B1
A3		 I/O Advanced control timer 1 CCR1 capture input or compare output
Timer (continued) TIMA1_C1N 9
19
53
55
59		 17
21
31
41		 13
20		 14
19		 8
12		 F2
E1		 I/O Advanced control timer 1 CCR1 compare output (inverting)
TIMA_FAL0 22
30
35
46		 3
12
46		 10
30		 1
13		 22 B3
G3
B2		 I Advanced control timer 0 fault handling input
TIMA_FAL1 19
33
45
64		 1
11
41		 1
9		 4
12		 24 D3
F3		 I Advanced control timer 1 fault handling input
TIMA_FAL2 27
31
34		 2
47		 2
31		 2
5		 1 C3
E3		 I Advanced control timer 2 fault handling input
UART UART0_TX 33
35
47
56		 1
3
18		 1
14		 4
15		 9
24		 D3
G1		 O UART0 transmit data
UART0_RX 34
39
48
57		 2
5
19		 2
15		 5
16		 1
10		 E3
G2		 I UART0 receive data
UART0_CTS 7
16
27
55		 17
29
38		 13
18		 14
17		 8 F2
A1		 I UART0 "clear to send" flow control input
UART0_RTS 8
28
54		 16
30		 12
19		 18 11 F1 O UART0 "request to send" flow control output
UART1_TX 10
52
54
58		 16
20
32		 12
21		 20 13 - O UART1 transmit data
UART1_RX 11
53
55
59		 17
21
33		 13
22		 14
21		 8
14		 F2
B1		 I UART1 receive data
UART1_CTS 17
50
60		 14
22
39		 25 24 17 D2 I UART1 "clear to send" flow control input
UART1_RTS 18
51
61		 15
23
40		 26 25 18 C2 O UART1 "request to send" flow control output
UART2_TX 3
14
17
24		 25
36
39
43		 25
27		 24
26		 17
19		 D2
A2		 O UART2 transmit data
UART2_RX 4
15
18
25		 26
37
40
44		 26
28		 25
27		 18
20		 C2
A3		 I UART2 receive data
UART2_CTS 37
43
50
58		 9
14
20		 7 10 6 F4 I UART2 "clear to send" flow control input
UART2_RTS 36
44
51
59		 10
15
21		 8 11 7 G4 O UART2 "request to send" flow control output
UART (continued) UART3_TX 7
30
50
64		 14
29
46		 18
30		 1
17		 22 B3 O UART3 transmit data
UART3_RX 1
6
26
51		 15
28
45		 17
29		 28 21 E2 I UART3 receive data
UART3_CTS 3
5
24
52		 25
27
43		 16
27		 26 19 A2 I UART3 "clear to send" flow control input
UART3_RTS 4
6
25
53		 26
28
44		 17
28		 27 20 A3 O UART3 "request to send" flow control output
Voltage Reference (3) VREF+ 24 43 27 26 19 A2 I/O Voltage reference (VREF) power supply; external reference input or internal reference output
VREF- 17 39 25 24 17 D2 I/O Voltage reference (VREF) ground supply; external reference input or internal reference output
(1) – = not available
(2) I = input, O = output, I/O = input or output, P = power
(3) When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source