SLASF11D February   2023  – October 2025 MSPM0G1105 , MSPM0G1106 , MSPM0G1107

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Ramp
      1. 7.6.1 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
        1. 7.9.1.1 SYSOSC Typical Frequency Accuracy
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
    13. 7.13 Typical Connection Diagram
    14. 7.14 Temperature Sensor
    15. 7.15 VREF
      1. 7.15.1 Voltage Characteristics
      2. 7.15.2 Electrical Characteristics
    16. 7.16 GPAMP
      1. 7.16.1 Electrical Characteristics
      2. 7.16.2 Switching Characteristics
    17. 7.17 I2C
      1. 7.17.1 I2C Timing Diagram
      2. 7.17.2 I2C Characteristics
      3. 7.17.3 I2C Filter
    18. 7.18 SPI
      1. 7.18.1 SPI
      2. 7.18.2 SPI Timing Diagram
    19. 7.19 UART
    20. 7.20 TIMx
    21. 7.21 Emulation and Debug
      1. 7.21.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0G110x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 GPAMP
    16. 8.16 CRC
    17. 8.17 UART
    18. 8.18 I2C
    19. 8.19 SPI
    20. 8.20 WWDT
    21. 8.21 RTC
    22. 8.22 Timers (TIMx)
    23. 8.23 Device Analog Connections
    24. 8.24 Input/Output Diagrams
    25. 8.25 Serial Wire Debug Interface
    26. 8.26 Bootstrap Loader (BSL)
    27. 8.27 Device Factory Constants
    28. 8.28 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGZ|48
  • PT|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.2 Pin Attributes

The following table describes the functions available on every pin for each device package.

Note: Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which allows users to configure the desired Pin Function using the PINCM.PF control bits.
Table 6-1 Digital IO Features by IO Type
IO STRUCTUREINVERSION CONTROLDRIVE STRENGTH CONTROLHYSTERESIS CONTROLPULLUP RESISTORPULLDOWN RESISTORWAKEUP LOGIC
Standard-driveYYY
Standard-drive with wake(1)YYYY
High-driveYYYYY
High-speedYYYY
5V-tolerant open drainYYYY
Table 6-2 Pin Attributes
PINCMxPIN NAMESIGNAL NAMESPIN NUMBERIO STRUCTURE
ANALOGDIGITAL [PIN FUNCTION] (1)64 LQFP48 LQFP, VQFN32 VQFN28 VSSOP24 VQFN28 DSBGA
N/AVDD406473C4Power
N/AVSS417584D4Power
N/AVCORE324832323A4Power
N/ANRST384362B4Reset
1PA0UART0_TX [2] / I2C0_SDA [3] / TIMA0_C0 [4] / TIMA_FAL1 [5] / TIMG8_C1 [6] / FCC_IN [7]/(Default BSL I2C_SDA)3311424D35V-tolerant open drain
2PA1UART0_RX [2] / I2C0_SCL [3] / TIMA0_C1 [4] / TIMA_FAL2 [5] / TIMG8_IDX [6] / TIMG8_C0 [7]/(Default BSL I2C_SCL)342251E35V-tolerant open drain
7PA2ROSCTIMG8_C1 [2] / SPI0_CS0 [3] / TIMG7_C1 [4] / SPI1_CS0 [5]428695E4Standard
8PA3LFXINTIMG8_C0 [2] / SPI0_CS1 [3] / UART2_CTS [4] / TIMA0_C2 [5] / COMP1_OUT [6] / TIMG7_C0 [7] / TIMA0_C1 [8] / I2C1_SDA [9] 4397106F4Standard
9PA4LFXOUTTIMG8_C1 [2] / SPI0_POCI [3] / UART2_RTS [4] / TIMA0_C3 [5] / LFCLK_IN [6] / TIMG7_C1 [7] / TIMA0_C1N [8] / I2C1_SCL [9]44108117G4Standard
10PA5HFXINTIMG8_C0 [2] / SPI0_PICO [3] / TIMA_FAL1 [4] / TIMG0_C0 [5]/ TIMG6_C0 [6] / FCC_IN [7]4511912-F3Standard
11PA6HFXOUTTIMG8_C1 [2] / SPI0_SCK [3] / TIMA_FAL0 [4] / TIMG0_C1 [5] / HFCLK_IN [6] / TIMG6_C1 [ 7] / TIMA0_C2N [8]46121013-G3Standard
14PA7CLK_OUT [3] / TIMG8_C0 [4] / TIMA0_C2 [5] / TIMG8_IDX [6] / TIMG7_C1 [7] / TIMA0_C1 [8]491311---Standard
19PA8UART1_TX [2] / SPI0_CS0 [3] / UART0_RTS [4] / TIMA0_C0 [5] / TIMA1_C0N [6]541612---Standard
20PA9UART1_RX [2] / SPI0_PICO [3] / UART0_CTS [4] / TIMA0_C1 [5] / RTC_OUT [6] / TIMA0_C0N [7] / TIMA1_C1N [8] / CLK_OUT [9]551713148F2High-Speed
21PA10UART0_TX [2] / SPI0_POCI [3] / I2C0_SDA [4] / TIMA1_C0 [5] / TIMG12_C0 [6] / TIMA0_C2 [7] / I2C1_SDA [8] / CLK_OUT [9]/(Default BSL UART_TX)561814159G1High-Drive
22PA11UART0_RX [2] / SPI0_SCK [3] / I2C0_SCL [4] / TIMA1_C1 [5] / COMP0_OUT [6]/ TIMA0_C2N [7] / I2C1_SCL [8]/(Default BSL UART_RX)5719151610G2High-Drive
34PA12UART3_CTS [2] / SPI0_SCK [3] / TIMG0_C0 [4] / TIMA0_C3 [6] / FCC_IN [7]52716---High-Speed
35PA13UART3_RTS [2] / SPI0_POCI [3] / UART3_RX [4] / TIMG0_C1 [5] / TIMA0_C3N [7]62817---High-Speed
36PA14A0_12UART0_CTS [2] / SPI0_PICO [3] / UART3_TX [4] / TIMG12_C0 [5] / CLK_OUT [6]7291817--High-Speed
37PA15A1_0 UART0_RTS [2] / SPI1_CS2 [3] / I2C1_SCL [4] / TIMA1_C0 [5] / TIMG8_IDX [6] / TIMA1_C0N [7] / TIMA0_C2 [8]830191811F1Standard
38PA16A1_1SPI1_POCI [3] / I2C1_SDA [4] / TIMA1_C1 [5] / TIMA1_C1N [6] / TIMA0_C2N [7] / FCC_IN [8]931201912E1Standard
39PA17A1_2UART1_TX [2] / SPI1_SCK [3] / I2C1_SCL [4] / TIMA0_C3 [5] / TIMG7_C0 [6] / TIMA1_C0 [7]1032212013-Standard with wake(2)
40PA18A1_3 / GPAMP_IN-UART1_RX [2] / SPI1_PICO [3] / I2C1_SDA [4] / TIMA0_C3N [5] / TIMG7_C1 [6] / TIMA1_C1 [7]/Default BSL_Invoke1133222114B1Standard with wake(2)
41PA19SWDIO [2]1234232215C1High-Speed
42PA20SWCLK [2]1335242316D1Standard
46PA21A1_7 / VREF-UART2_TX [2] / TIMG8_C0 [3] / UART1_CTS [4] / TIMA0_C0 [5] / TIMG6_C0 [6]1739252417D2Standard
47PA22A0_7 / GPAMP_OUTUART2_RX [2] / TIMG8_C1 [3] / UART1_RTS [4] / TIMA0_C1 [5] / CLK_OUT [6] / TIMA0_C0N [7] / TIMG6_C1 [8]1840262518C2Standard
53PA23VREF+UART2_TX [2] / SPI0_CS3 [3] / TIMA0_C3 [4] / TIMG0_C0 [5] / UART3_CTS [6] / TIMG7_C0 [7]/ TIMG8_C0 [8]2443272619A2Standard
54PA24A0_3UART2_RX [2] / SPI0_CS2 [3] / TIMA0_C3N [4] / TIMG0_C1 [5] / UART3_RTS [6] / TIMG7_C1 [7] / TIMA1_C1 [8]2544282720A3Standard
55PA25A0_2 UART3_RX [2] / SPI1_CS3 [3] / TIMG12_C1 [4] / TIMA0_C3 [5] / TIMA0_C1N [6]2645292821E2Standard
59PA26A0_1 / GPAMP_IN+UART3_TX [2] / SPI1_CS0 [3] / TIMG8_C0 [4] / TIMA_FAL0 [5] / TIMG7_C0 [7]304630122B3Standard
60PA27A0_0RTC_OUT [2] / SPI1_CS1 [3] / TIMG8_C1 [4] / TIMA_FAL2 [5] / TIMG7_C1 [7]3147312-C3Standard
3PA28UART0_TX [2] / I2C0_SDA [3] / TIMA0_C3 [4] / TIMA_FAL0 [5] / TIMG7_C0 [6] / TIMA1_C0 [ 7]353----High-Drive
4PA29I2C1_SCL [2] / UART2_RTS [3] / TIMG8_C0 [4] / TIMG6_C0 [5]36-----Standard
5PA30I2C1_SDA [2] / UART2_CTS [3] / TIMG8_C1 [4] / TIMG6_C1 [5]37-----Standard
6PA31UART0_RX [2] / I2C0_SCL [3] / TIMA0_C3N [4] / TIMG12_C1 [5] / CLK_OUT [6]/ TIMG7_C1 [7] / TIMA1_C1 [8]395----High-Drive
12PB0UART0_TX [2] / SPI1_CS2 [3] / TIMA1_C0 [4] / TIMA0_C2 [5]47-----Standard
13PB1UART0_RX [2] / SPI1_CS3 [3] / TIMA1_C1 [4] / TIMA0_C2N [5]48––---Standard
15PB2UART3_TX [2] / UART2_CTS [3] / I2C1_SCL [4] / TIMA0_C3 [5] / UART1_CTS [6] / TIMG6_C0 [ 7] / TIMA1_C0 [8]5014–---Standard
16PB3UART3_RX [2] / UART2_RTS [3] / I2C1_SDA [4] / TIMA0_C3N[5] / UART1_RTS [6] / TIMG6_C1 [7] / TIMA1_C1 [8]5115–---Standard
17PB4UART1_TX [2] / UART3_CTS [3] / TIMA1_C0 [4] /TIMA0_C2 [5] / TIMA1_C0N [6]52––---Standard
18PB5UART1_RX [2] / UART3_RTS [3] / TIMA1_C1 [4] / TIMA0_C2N [5] / TIMA1_C1N [6]53-----Standard
23PB6UART1_TX [2] / SPI1_CS0 [3] / SPI0_CS1 [4] / TIMG8_C0 [5] / UART2_CTS [6] / TIMG6_C0 [7] / TIMA1_C0N [8]5820----Standard
24PB7UART1_RX [2] / SPI1_POCI [3] / SPI0_CS2 [4] / TIMG8_C1 [5] / UART2_RTS [6] / TIMG6_C1 [7] /TIMA1_C1N [8]5921----Standard
25PB8UART1_CTS [2] / SPI1_PICO [3] / TIMA0_C0 [4] / COMP1_OUT [5]6022----Standard
26PB9UART1_RTS [2] / SPI1_SCK [3] / TIMA0_C1 [4] / TIMA0_C0N [5]6123----Standard
27PB10TIMG0_C0 [2] / TIMG8_C0 [3] / COMP1_OUT [4] / TIMG6_C0 [5]62-----Standard
28PB11TIMG0_C1 [2] / TIMG8_C1 [3] / CLK_OUT [4] / TIMG6_C1 [5]63-----Standard
29PB12UART3_TX [2] / TIMA0_C2 [3] / TIMA_FAL1 [4] / TIMA0_C1 [5]64-----Standard
30PB13UART3_RX [2] / TIMA0_C3 [3] / TIMG12_C0 [4] / TIMA0_C1N [5]1-----Standard
31PB14SPI1_CS3 [2] / SPI1_POCI [3] / SPI0_CS3 [4] / TIMG12_C1 [5] / TIMG8_IDX [6] / TIMA0_C0 [7]224----Standard
32PB15UART2_TX [2] / SPI1_PICO [3] / UART3_CTS [4] / TIMG8_C0 [5] / TIMG7_C0 [6]325----Standard
33PB16UART2_RX [2] / SPI1_SCK [3] / UART3_RTS [4] / TIMG8_C1 [5] / TIMG7_C1 [6]426----Standard
43PB17A1_4UART2_TX [2] / SPI0_PICO [3] / SPI1_CS1 [4] / TIMA1_C0 [5] / TIMA0_C2 [6]1436----Standard
44PB18A1_5 UART2_RX [2] / SPI0_SCK [3] / SPI1_CS2 [4] / TIMA1_C1 [5] / TIMA0_C2N [6]1537----Standard
45PB19A1_6 SPI0_POCI [3] / TIMG8_C1 [4] / UART0_CTS [5] / TIMG7_C1 [6]1638---A1Standard
48PB20A0_6SPI0_CS2 [2] / SPI1_CS0 [3] / TIMA0_C2 [4] / TIMG12_C0 [5] / TIMA_FAL1 [6] / TIMA0_C1 [7] / TIMA1_C1N [8]1941----Standard
49PB21SPI1_POCI [2] / TIMG8_C0 [3]20-----Standard
50PB22SPI1_PICO [2] / TIMG8_C1 [3]21-----Standard
51PB23SPI1_SCK [2] / COMP0_OUT [3] / TIMA_FAL0 [4]22----B2Standard
52PB24A0_5SPI0_CS3 [2] / SPI0_CS1 [3] / TIMA0_C3 [4] / TIMG12_C1 [5] / TIMA0_C1N [6] / TIMA1_C0N [7]2342----Standard
56PB25A0_4UART0_CTS [2] / SPI0_CS0 [3] / TIMA_FAL2 [4]27-----Standard
57PB26UART0_RTS [2] / SPI0_CS1 [3] / TIMA0_C3 [4] / TIMG6_C0 [5] 28-----Standard
58PB27 SPI1_CS1 [3] / TIMA0_C3N [4] / TIMG6_C1 [5] / TIMA1_C1 [6]29-----Standard
(1) Set PINCM.PF and PINCM.PC in IOMUX to 0 for analog functions (for example, OPA inputs/outputs or COMP inputs). Each digital I/O on a device is mapped to a specific Pin Control Management register (PINCMx) that lets users configure the desired pin function using the PINCM.PF control bits.
(2) Standard with Wake allows the I/O to wake up the device from the lowest low-power mode of SHUTDOWN. All I/O can be configured to wakeup the MCU from higher low-power modes. See section GPIO FastWake in the MSPM0 G-Series 80MHz Microcontrollers Technical Reference Manual for details.
(1) Standard with Wake allows the I/O to wake up the device from the lowest low-power mode of SHUTDOWN. All I/O can be configured to wakeup the MCU from higher low-power modes. See section GPIO FastWake in the MSPM0 G-Series 80MHz Microcontrollers Technical Reference Manual for details.