SLASEW9E February   2023  – October 2025 MSPM0G1505 , MSPM0G1506 , MSPM0G1507

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
        1. 7.6.1.1 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 SYSOSC Typical Frequency Accuracy
        1. 7.9.2.1 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
    13. 7.13 Typical Connection Diagram
    14. 7.14 Temperature Sensor
    15. 7.15 VREF
      1. 7.15.1 Voltage Characteristics
      2. 7.15.2 Electrical Characteristics
    16. 7.16 Comparator (COMP)
      1. 7.16.1 Comparator Electrical Characteristics
    17. 7.17 DAC
      1. 7.17.1 DAC_Supply Specifications
      2. 7.17.2 DAC Output Specifications
      3. 7.17.3 DAC Dynamic Specifications
      4. 7.17.4 DAC Linearity Specifications
      5. 7.17.5 DAC Timing Specifications
    18. 7.18 GPAMP
      1. 7.18.1 Electrical Characteristics
      2. 7.18.2 Switching Characteristics
    19. 7.19 OPA
      1. 7.19.1 Electrical Characteristics
      2. 7.19.2 Switching Characteristics
      3. 7.19.3 PGA Mode
    20. 7.20 I2C
      1. 7.20.1 I2C Characteristics
      2. 7.20.2 I2C Filter
        1. 7.20.2.1 I2C Timing Diagram
    21. 7.21 SPI
      1. 7.21.1 SPI
      2. 7.21.2 SPI Timing Diagram
    22. 7.22 UART
    23. 7.23 TIMx
    24. 7.24 TRNG
      1. 7.24.1 TRNG Electrical Characteristics
      2. 7.24.2 TRNG Switching Characteristics
    25. 7.25 Emulation and Debug
      1. 7.25.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0G150x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 COMP
    16. 8.16 DAC
    17. 8.17 OPA
    18. 8.18 GPAMP
    19. 8.19 TRNG
    20. 8.20 AES
    21. 8.21 CRC
    22. 8.22 UART
    23. 8.23 I2C
    24. 8.24 SPI
    25. 8.25 WWDT
    26. 8.26 RTC
    27. 8.27 Timers (TIMx)
    28. 8.28 Device Analog Connections
    29. 8.29 Input/Output Diagrams
    30. 8.30 Serial Wire Debug Interface
    31. 8.31 Bootstrap Loader (BSL)
    32. 8.32 Device Factory Constants
    33. 8.33 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1 Functionality by Operating Mode (MSPM0G150x)

Supported functionality in each operating mode is given in Table 8-1.

Functional key:

  • EN: The function is enabled in the specified mode.
  • DIS: The function is disabled (either clock or power gated) in the specified mode, but the function's configuration is retained.
  • OPT: The function is optional in the specified mode and remains enabled if configured to be enabled.
  • NS: The function is not automatically disabled in the specified mode, but use of the function is not supported.
  • OFF: The function is fully powered off in the specified mode, and no configuration information is retained. When waking up from an OFF state, all module registers must be reconfigured to the desired settings by application software.
Table 8-1 Supported Functionality by Operating Mode
OPERATING MODERUNSLEEPSTOPSTANDBYSHUTDOWN
RUN0RUN1RUN2SLEEP0SLEEP1SLEEP2STOP0STOP1STOP2STANDBY0STANDBY1
OscillatorsSYSOSCENDISENDISOPT(1)ENDISDISOFF
LFOSC or LFXTEN (LFOSC or LFXT)OFF
HFXTOPTDISOPTDISDISDISOFF
SYSPLLOPTDIS(4)OPTDIS(4)DIS(4)DIS(4)OFF
ClocksCPUCLK80MHz32KHzDISOFF
MCLK to PD180MHz32KHz80MHz32KHzDISOFF
ULPCLK to PD040MHz32KHz40MHz32KHz4MHz(1)4MHz32KHz32KHzDISOFF
ULPCLK to TIMG0/840MHz32KHz40MHz32KHz4MHz(1)4MHz32KHz32KHz32KHz(2)OFF
RTCCLK32KHzOFF
MFCLKOPTDISOPTDISOPTDISDISOFF
MFPCLKOPTDISOPTDISOPTDISDISOFF
LFCLK to PD0/132KHzDISOFF
LFCLK to TIMG0/832KHz32KHz(2)OFF
LFCLK MonitorOPTOFF
MCLK MonitorOPTDISOFF
PMUPOR monitorEN
BOR monitorENOFF
Core regulatorFULL DRIVEREDUCED DRIVELOW DRIVEOFF
Core FunctionsCPUENDISOFF
DMAOPTDIS (triggers supported)OFF
FlashENDISOFF
SRAMENDISOFF
PD1 Peripherals

MATHACL

OPTOFFOFF
UART3OPT

DIS

OFF

SPI0/1OPT

DIS

OFF

TIMA0/1OPTOFFOFF
TIMG6/7/12OPTOFFOFF
AESOPTOFFOFF
CRCOPTDISOFF
TRNGOPTOFFOFF
PD0 PeripheralsGPIOA/B(3)OPTOPT(2)OFF
UART0/1/2OPTOPT(2)OFF
I2C0/1OPTOPT(2)OFF
TIMG0/8OPTOPT(2)OFF
WWDT0/1OPTDISOFF
RTCOPTOFF
AnalogVREFOPTOFF
ADC0/1(3)OPTNS (triggers supported)OFF
COMP0/1/2OPTOPT (ULP)OPTOPT (ULP)OPTOPT (ULP)OFF
OPA0/1OPTNSOPTNSOPTNSOFF
DAC0OPTNSOFF
GPAMPOPTNSOFF
TEMP SensorOPTOFFOFF
IOMUX and IO WakeupENDIS w/ WAKE
Wake SourcesN/AANY IRQPD0 IRQIOMUX, NRST, SWD
(1) If STOP0 is entered from RUN1 (SYSOSC enabled but MCLK sourced from LFCLK), SYSOSC remains enabled as it was in RUN1, and ULPCLK remains at 32KHz as it was in RUN1. If STOP0 is entered from RUN2 (SYSOSC was disabled and MCLK was sourced from LFCLK), SYSOSC remains disabled as it was in RUN2, and ULPCLK remains at 32KHz as it was in RUN2.
(2) When using the STANDBY1 policy for STANDBY, only specific peripherals (TIMG0, TIMG8, and RTC) are clocked. Other PD0 peripherals can generate an asynchronous fast clock request upon external activity but are not actively clocked.
(3) For ADCx and GPIO Ports A and B, the digital logic is in PD0 and the register interface is in PD1. These peripherals support fast single-cycle register access when PD1 is active and also support basic operation down to STANDBY mode where PD0 is still active.
(4) SYSPLL is not automatically disabled, and needs to be manually disabled through the HSCLKEN.SYSPLLEN field within the SYSCTL registers in order to reduce power consumption.