SBOS701D December   2015  – August 2021 OPA191 , OPA2191 , OPA4191

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA191
    5. 6.5 Thermal Information: OPA2191
    6. 6.6 Thermal Information: OPA4191
    7. 6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V)
    8. 6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V)
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Input Offset Voltage Drift
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Protection Circuitry
      2. 8.3.2 EMI Rejection
      3. 8.3.3 Phase Reversal Protection
      4. 8.3.4 Thermal Protection
      5. 8.3.5 Capacitive Load and Stability
      6. 8.3.6 Common-Mode Voltage Range
      7. 8.3.7 Electrical Overstress
      8. 8.3.8 Overload Recovery
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Low-side Current Measurement
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 16-Bit Precision Multiplexed Data-Acquisition System
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Slew Rate Limit for Input Protection
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 TINA-TI™ SImulation Software (Free Download)
        2. 12.1.1.2 TI Precision Designs
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-66EE3B20-D24F-484A-8480-2D70770EED38-low.gifFigure 5-1 OPA191 DBV (5-Pin SOT) Package,
Top View
GUID-24EA4D66-134E-4728-9068-F32AB4CBD320-low.gifFigure 5-2 OPA191 D (8-Pin SOIC) and
DGK (8-Pin VSSOP) Packages, Top View
Pin Functions: OPA191
PIN I/O DESCRIPTION
NAME OPA191
D (SOIC),
DGK (VSSOP)		 DBV (SOT)
+IN 3 3 I Noninverting input
–IN 2 4 I Inverting input
NC 1, 5, 8 — — No internal connection (can be left floating)
OUT 6 1 O Output
V+ 7 5 — Positive (highest) power supply
V– 4 2 — Negative (lowest) power supply
GUID-B557BF49-E24B-4A27-837D-9296AF6FFE5E-low.gifFigure 5-3 OPA2191 D (8-Pin SOIC) and
DGK (8-Pin VSSOP) Packages, Top View
GUID-6FB4124F-F4AF-49A4-ABAF-8888D1353400-low.gifFigure 5-4 OPA4191 D (14-Pin SOIC) and
PW (14-Pin TSSOP) Packages, Top View
GUID-4D00CD7D-EC54-4BEB-BB4D-098CAD055922-low.gifFigure 5-5 OPA4191 RUM (16-Pin WQFN With Exposed Thermal Pad) Package, Top View
Pin Functions: OPA2191 and OPA4191
PIN I/O DESCRIPTION
NAME OPA2191 OPA4191
D (SOIC),
DGK (VSSOP)		 D (SOIC),
PW (TSSOP)		 RUM (QFN)
+IN A 3 3 2 I Noninverting input, channel A
+IN B 5 5 4 I Noninverting input, channel B
+IN C — 10 9 I Noninverting input, channel C
+IN D — 12 11 I Noninverting input, channel D
–IN A 2 2 1 I Inverting input, channel A
–IN B 6 6 5 I Inverting input, channel B
–IN C — 9 8 I Inverting input,,channel C
–IN D — 13 12 I Inverting input, channel D
OUT A 1 1 15 O Output, channel A
OUT B 7 7 6 O Output, channel B
OUT C — 8 7 O Output, channel C
OUT D — 14 14 O Output, channel D
V+ 8 4 3 — Positive (highest) power supply
V– 4 11 10 — Negative (lowest) power supply