SBOS701D Data sheet

SBOS701D December 2015 – August 2021 OPA191 , OPA2191 , OPA4191

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

D|8
- MSOI002K
DGK|8
- MPDS028D

Thermal pad, mechanical data (Package|Pins)

D|8
- QFND304D
DGK|8
- QFND519

Orderable Information

6.9 Typical Characteristics

at T_A = 25°C, V_S = ±18 V, V_CM = V_S / 2, R_L = 10 kΩ connected to V_S / 2, and C_L = 100 pF (unless otherwise noted)

Table 6-1 Table of Graphs

DESCRIPTION	FIGURE
Offset Voltage Production Distribution	Figure 6-1, Figure 6-2, Figure 6-3, Figure 6-4, Figure 6-5, Figure 6-6
Offset Voltage Drift Distribution	Figure 6-7, Figure 6-8,
Offset Voltage vs Temperature	Figure 6-9, Figure 6-10
Offset Voltage vs Common-Mode Voltage	Figure 6-11, Figure 6-12
Offset Voltage vs Power Supply	Figure 6-13
Open-Loop Gain and Phase vs Frequency	Figure 6-14
Closed-Loop Gain and Phase vs Frequency	Figure 6-15
Input Bias Current vs Common-Mode Voltage	Figure 6-16
Input Bias Current vs Temperature	Figure 6-17
Output Voltage Swing vs Output Current (maximum supply)	Figure 6-18, Figure 6-19
CMRR and PSRR vs Frequency	Figure 6-20
CMRR vs Temperature	Figure 6-21
PSRR vs Temperature	Figure 6-22
0.1-Hz to 10-Hz Noise	Figure 6-23
Input Voltage Noise Spectral Density vs Frequency	Figure 6-24
THD+N Ratio vs Frequency	Figure 6-25
THD+N vs Output Amplitude	Figure 6-26
Quiescent Current vs Supply Voltage	Figure 6-27
Quiescent Current vs Temperature	Figure 6-28
Open Loop Gain vs Temperature	Figure 6-29, Figure 6-30
Open Loop Output Impedance vs Frequency	Figure 6-31
Small Signal Overshoot vs Capacitive Load (100-mV output step)	Figure 6-32, Figure 6-33
No Phase Reversal	Figure 6-34
Overload Recovery	Figure 6-35
Small-Signal Step Response (100 mV)	Figure 6-36, Figure 6-37
Large-Signal Step Response	Figure 6-38, Figure 6-39
Settling Time	Figure 6-40, Figure 6-41, Figure 6-42, Figure 6-43
Short-Circuit Current vs Temperature	Figure 6-44
Maximum Output Voltage vs Frequency	Figure 6-45
Propagation Delay Rising Edge	Figure 6-46
Propagation Delay Falling Edge	Figure 6-47

T_A = 25°C

Figure 6-1 Offset Voltage Production Distribution

T_A = 85°C

Figure 6-3 Offset Voltage Production Distribution

T_A = –25°C

Figure 6-5 Offset Voltage Production Distribution

T_A = –40°C to +125°C, SOIC package

Figure 6-7 Offset Voltage Drift Distribution

Statistical distribution

Figure 6-9 Offset Voltage vs Temperature

Figure 6-11 Offset Voltage vs Common-Mode Voltage

30 typical units

Figure 6-13 Offset Voltage vs Power Supply

Figure 6-15 Closed-Loop Gain vs Frequency

Figure 6-17 Input Bias Current vs Temperature

Sinking

Figure 6-19 Output Voltage Swing
vs Output Current

Figure 6-21 CMRR vs Temperature

Figure 6-23 0.1-Hz to 10-Hz Noise

Figure 6-25 THD+N vs Frequency

Figure 6-27 Quiescent Current vs Supply Voltage

R_L = 10 kΩ

Figure 6-29 Open-Loop Gain vs Temperature

Figure 6-31 Open-Loop Output Impedance
vs Frequency

G = –1, 100-mV output step

Figure 6-33 Small-Signal Overshoot
vs Capacitive Load

V_S = ±18 V, G = –10 V/V

Figure 6-35 Overload Recovery

G = –1, R_L = 1 kΩ, C_L = 10 pF

Figure 6-37 Small-Signal Step Response

G = –1, R_L = 1 kΩ, C_L = 10 pF

Figure 6-39 Large-Signal Step Response

Gain = 1, 2-V step, falling, step applied at t = 0 µs

Figure 6-41 0.01% Settling Time

Gain = 1, 5-V step, falling, step applied at t = 0 µs

Figure 6-43 0.01% Settling Time

Figure 6-45 Maximum Output Voltage vs Frequency

Figure 6-47 Propagation Delay Falling Edge

T_A = 125°C

Figure 6-2 Offset Voltage Production Distribution

T_A = 0°C

Figure 6-4 Offset Voltage Production Distribution

T_A = –40°C

Figure 6-6 Offset Voltage Production Distribution

T_A = 0°C to 85°C, SOIC package

Figure 6-8 Offset Voltage Drift Distribution

4 typical units

Figure 6-10 Offset Voltage vs Temperature

Figure 6-12 Offset Voltage vs Common-Mode Voltage in Transition Region

Figure 6-14 Open-Loop Gain and Phase
vs Frequency

Figure 6-16 Input Bias Current
vs Common-Mode Voltage

Sourcing

Figure 6-18 Output Voltage Swing
vs Output Current

Figure 6-20 CMRR and PSRR vs Frequency

Figure 6-22 PSRR vs Temperature

Figure 6-24 Input Voltage Noise Spectral Density vs Frequency

Figure 6-26 THD+N vs Output Amplitude

Figure 6-28 Quiescent Current vs Temperature

R_L = 2 kΩ

Figure 6-30 Open-Loop Gain vs Temperature

G = 1, 100-mV output step

Figure 6-32 Small-Signal Overshoot
vs Capacitive Load (100-mV Output Step)

Figure 6-34 No Phase Reversal

G = 1, C_L = 10 pF

Figure 6-36 Small-Signal Step Response

G = 1, C_L = 10 pF

Figure 6-38 Large-Signal Step Response

Gain = 1, 2-V step, rising, step applied at t = 0 µs

Figure 6-40 0.01% Settling Time

Gain = 1, 5-V step, rising, step applied at t = 0 µs

Figure 6-42 0.01% Settling Time

Figure 6-44 Short-Circuit Current vs Temperature

Figure 6-46 Propagation Delay Rising Edge