SBOS637D October   2016  – June 2019 OPA2325 , OPA325 , OPA4325

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Offset Voltage vs Input Common-Mode Voltage
  3. 3 Description
    1.     The OPAx325 as an ADC Driver Amplifier
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions: OPA325
    2.     Pin Functions: OPA2325
    3.     Pin Functions: OPA4325
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA325
    5. 6.5 Thermal Information: OPA2325
    6. 6.6 Thermal Information: OPA4325
    7. 6.7 Electrical Characteristics: VS = 2.2 V to 5.5 V or ±1.1 V to ±2.75 V
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Zero-Crossover Input Stage
      2. 7.3.2 Low Input Offset Voltage
      3. 7.3.3 Input and ESD Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Operating Characteristics
      2. 8.1.2 Basic Amplifier Configurations
      3. 8.1.3 Driving an Analog-to-Digital Converter
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:

  • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry.
    • Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-supply applications.
  • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information refer to, see Circuit Board Layout Techniques.
  • In order to reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace.
  • Place the external components as close as possible to the device. As illustrated in Figure 57, keeping RF and RG close to the inverting input minimizes parasitic capacitance.
  • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
  • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.
  • For best performance, clean the PCB following board assembly.
  • Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.