SLLS530C April   2002  – February 2019 SN65LVDT14 , SN65LVDT41

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      SN65LVDT41 Functional Diagram
      2.      SN65LVDT14 Functional Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     SN65LVDT41 Pin Functions
    2.     SN65LVDT14 Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Receiver Electrical Characteristics
    6. 6.6  Driver Electrical Characteristics
    7. 6.7  Device Electrical Characteristics
    8. 6.8  Receiver Switching Characteristics
    9. 6.9  Driver Switching Characteristics
    10. 6.10 Typical Characteristics
      1. 6.10.1 Receiver
      2. 6.10.2 Driver
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 SN65LVDTxx Driver and Receiver Functionality
      2. 8.3.2 Integrated Termination
      3. 8.3.3 SN65LVDTxx Equivalent Circuits
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Extending a Serial Peripheral Interface Using LVDS Signaling Over Differential Transmission Cables
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 SPI Propagation Delay Limitations
        2. 9.2.2.2 Interconnecting Media
        3. 9.2.2.3 Input Fail-Safe Biasing
        4. 9.2.2.4 Power Decoupling Recommendations
        5. 9.2.2.5 PCB Transmission Lines
        6. 9.2.2.6 Probing LVDS Transmission Lines on PCB
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Microstrip vs. Stripline Topologies
      2. 11.1.2 Dielectric Type and Board Construction
      3. 11.1.3 Recommended Stack Layout
      4. 11.1.4 Separation Between Traces
      5. 11.1.5 Crosstalk and Ground Bounce Minimization
      6. 11.1.6 Decoupling
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

SN65LVDT14 SN65LVDT41 vdef_lls530.gifFigure 8. Receiver Voltage Definitions

Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages

APPLIED VOLTAGES RESULTING DIFFERENTIAL
INPUT VOLTAGE		 RESULTING
COMMON-MODE
INPUT VOLTAGE
VIA VIB VID VIC
1.25 V 1.15 V 100 mV 1.2 V
1.15 V 1.25 V –100 mV 1.2 V
2.4 V 2.3 V 100 mV 2.35 V
2.3 V 2.4 V –100 mV 2.35 V
0.1 V 0.0 V 100 mV 0.05 V
0.0 V 0.1 V –100 mV 0.05 V
1.5 V 0.9 V 600 mV 1.2 V
0.9 V 1.5 V –600 mV 1.2 V
2.4 V 1.8 V 600 mV 2.1 V
1.8 V 2.4 V –600 mV 2.1 V
0.6 V 0.0 V 600 mV 0.3 V
0.0 V 0.6 V –600 mV 0.3 V
SN65LVDT14 SN65LVDT41 cdef_lls530.gifFigure 9. Driver Voltage and Current Definitions
SN65LVDT14 SN65LVDT41 pmi_ttest_lls530.gifFigure 10. Receiver Timing Test Circuit
SN65LVDT14 SN65LVDT41 pmi_wave_lls530.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 1 Mpps, pulse width = 0.5 ± 0.05 µs. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 11. Receiver Timing Test Circuit Waveforms
SN65LVDT14 SN65LVDT41 pmi_dtcir_lls530.gifFigure 12. Driver VDO Test Circuit
SN65LVDT14 SN65LVDT41 pmi_ovolt_lls530.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0.06 mm of the D.U.T. The measurement of VOC(PP) is made on test equipment with a –3-dB bandwidth of at least 1 GHz.
Figure 13. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
SN65LVDT14 SN65LVDT41 pmi_osig_lls530.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 1 Mpps, pulse width = 0.5 ± 0.05 µs. CL includes instrumentation and fixture capacitance within 0.06 mm of the D.U.T.
Figure 14. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal