SCLS402O April   1998  – November 2016 SN74LV165A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements—VCC = 2.5 V ± 0.2 V
    7. 6.7  Timing Requirements—VCC = 3.3 V ± 0.3 V
    8. 6.8  Timing Requirements—VCC = 5 V ± 0.5 V
    9. 6.9  Switching Characteristics—VCC = 2.5 V ± 0.2 V
    10. 6.10 Switching Characteristics—VCC = 3.3 V ± 0.3 V
    11. 6.11 Switching Characteristics—VCC = 5 V ± 0.5 V
    12. 6.12 Operating Characteristics
    13. 6.13 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 10.5 ns at 5 V
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Ioff Supports Partial-Power-Down Mode
    Operation
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Applications

  • IP Routers
  • Enterprise Switches
  • Access Control and Security: Access Keypads and Biometrics
  • Smart Meters: Power Line Communication

Description

The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation.

When the devices are clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. The ’LV165A devices feature a clock-inhibit function and a complemented serial output, QH.

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and clock inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH accomplishes clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. The parallel inputs to the register are enabled while SH/LD is held low, independently of the levels of CLK, CLK INH, or SER.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SNx4LV165AD SOIC (16) 9.90 mm × 3.91 mm
SNx4LV165ADB SSOP (16) 6.20 mm × 5.30 mm
SNx4LV165ANS SO (16) 10.30 mm × 5.30 mm
SNx4LV165APW TSSOP (16) 5.00 mm × 4.40 mm
SNx4LV165ADGV TVSOP (16) 3.60 mm × 4.40 mm
SNx4LV165ARGY VQFN (16) 4.00 mm × 3.50 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram (Positive Logic)

SN54LV165A SN74LV165A ld_cls402.gif