The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V
When the devices are clocked, data is shifted toward the serial output
QH. Parallel-in access to each stage is provided by eight individual direct
data inputs that are enabled by a low level at the shift/load (SH/LD) input.
The ’LV165A devices feature a clock-inhibit function and a complemented serial output,
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while
SH/LD is held high and clock inhibit (CLK INH) is held low. The functions of
CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH
accomplishes clocking, CLK INH must be changed to the high level only while CLK is high. Parallel
loading is inhibited when SH/LD is held high. The parallel inputs to the
register are enabled while SH/LD is held low, independently of the levels of
CLK, CLK INH, or SER.
These devices are fully specified for partial-power-down applications using
Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the devices when they are powered down.