SNLS698A Data sheet

SNLS698A April 2021 – September 2023 TDES960

PRODUCTION DATA

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Mechanical Data (Package|Pins)

RTD|64
- MPQF141C

Thermal pad, mechanical data (Package|Pins)

Orderable Information

snls698a_oa

7.6.1 Main Registers

Table 7-20 lists the memory-mapped registers for the Main registers. All register offset addresses not listed in Table 7-20 should be considered as reserved locations and the register contents should not be modified.

Table 7-20 MAIN Registers

Address	Acronym	Register Name	Section
0x0	I2C_DEVICE_ID	I2C_DEVICE_ID	Go
0x1	RESET_CTL	RESET_CTL	Go
0x2	GENERAL_CFG	GENERAL_CFG	Go
0x3	REV_MASK_ID	REV_MASK_ID	Go
0x4	DEVICE_STS	DEVICE_STS	Go
0x5	PAR_ERR_THOLD_HI	PAR_ERR_THOLD_HI	Go
0x6	PAR_ERR_THOLD_LO	PAR_ERR_THOLD_LO	Go
0x7	BCC_WATCHDOG_CONTROL	BCC_WATCHDOG_CONTROL	Go
0x8	I2C_CONTROL_1	I2C_CONTROL_1	Go
0x9	I2C_CONTROL_2	I2C_CONTROL_2	Go
0xA	SCL_HIGH_TIME	SCL_HIGH_TIME	Go
0xB	SCL_LOW_TIME	SCL_LOW_TIME	Go
0xC	RX_PORT_CTL	RX_PORT_CTL	Go
0xD	IO_CTL	IO_CTL	Go
0xE	GPIO_PIN_STS	GPIO_PIN_STS	Go
0xF	GPIO_INPUT_CTL	GPIO_INPUT_CTL	Go
0x10	GPIO0_PIN_CTL	GPIO0_PIN_CTL	Go
0x11	GPIO1_PIN_CTL	GPIO1_PIN_CTL	Go
0x12	GPIO2_PIN_CTL	GPIO2_PIN_CTL	Go
0x13	GPIO3_PIN_CTL	GPIO3_PIN_CTL	Go
0x14	GPIO4_PIN_CTL	GPIO4_PIN_CTL	Go
0x15	GPIO5_PIN_CTL	GPIO5_PIN_CTL	Go
0x16	GPIO6_PIN_CTL	GPIO6_PIN_CTL	Go
0x17	GPIO7_PIN_CTL	GPIO7_PIN_CTL	Go
0x18	FS_CTL	FS_CTL	Go
0x19	FS_HIGH_TIME_1	FS_HIGH_TIME_1	Go
0x1A	FS_HIGH_TIME_0	FS_HIGH_TIME_0	Go
0x1B	FS_LOW_TIME_1	FS_LOW_TIME_1	Go
0x1C	FS_LOW_TIME_0	FS_LOW_TIME_0	Go
0x1D	MAX_FRM_HI	MAX_FRM_HI	Go
0x1E	MAX_FRM_LO	MAX_FRM_LO	Go
0x1F	CSI_PLL_CTL	CSI_PLL_CTL	Go
0x20	FWD_CTL1	FWD_CTL1	Go
0x21	FWD_CTL2	FWD_CTL2	Go
0x22	FWD_STS	FWD_STS	Go
0x23	INTERRUPT_CTL	INTERRUPT_CTL	Go
0x24	INTERRUPT_STS	INTERRUPT_STS	Go
0x25	TS_CONFIG	TS_CONFIG	Go
0x26	TS_CONTROL	TS_CONTROL	Go
0x27	TS_LINE_HI	TS_LINE_HI	Go
0x28	TS_LINE_LO	TS_LINE_LO	Go
0x29	TS_STATUS	TS_STATUS	Go
0x2A	TIMESTAMP_P0_HI	TIMESTAMP_P0_HI	Go
0x2B	TIMESTAMP_P0_LO	TIMESTAMP_P0_LO	Go
0x2C	TIMESTAMP_P1_HI	TIMESTAMP_P1_HI	Go
0x2D	TIMESTAMP_P1_LO	TIMESTAMP_P1_LO	Go
0x2E	TIMESTAMP_P2_HI	TIMESTAMP_P2_HI	Go
0x2F	TIMESTAMP_P2_LO	TIMESTAMP_P2_LO	Go
0x30	TIMESTAMP_P3_HI	TIMESTAMP_P3_HI	Go
0x31	TIMESTAMP_P3_LO	TIMESTAMP_P3_LO	Go
0x32	CSI_PORT_SEL	CSI_PORT_SEL	Go
0x33	CSI_CTL	CSI_CTL	Go
0x34	CSI_CTL2	CSI_CTL2	Go
0x35	CSI_STS	CSI_STS	Go
0x36	CSI_TX_ICR	CSI_TX_ICR	Go
0x37	CSI_TX_ISR	CSI_TX_ISR	Go
0x41	SFILTER_CFG	SFILTER_CFG	Go
0x42	AEQ_CTL	AEQ_CTL	Go
0x43	AEQ_ERR_THOLD	AEQ_ERR_THOLD	Go
0x46	BCC_ERR_CTL	BCC_ERR_CTL	Go
0x47	BCC_STATUS	BCC_STATUS	Go
0x4A	V3LINK_CAP	V3LINK_CAP	Go
0x4B	RAW_EMBED_DTYPE	RAW_EMBED_DTYPE	Go
0x4C	V3LINK_PORT_SEL	V3LINK_PORT_SEL	Go
0x4D	RX_PORT_STS1	RX_PORT_STS1	Go
0x4E	RX_PORT_STS2	RX_PORT_STS2	Go
0x4F	RX_FREQ_HIGH	RX_FREQ_HIGH	Go
0x50	RX_FREQ_LOW	RX_FREQ_LOW	Go
0x51	SENSOR_STS_0	SENSOR_STS_0	Go
0x52	SENSOR_STS_1	SENSOR_STS_1	Go
0x53	SENSOR_STS_2	SENSOR_STS_2	Go
0x54	SENSOR_STS_3	SENSOR_STS_3	Go
0x55	RX_PAR_ERR_HI	RX_PAR_ERR_HI	Go
0x56	RX_PAR_ERR_LO	RX_PAR_ERR_LO	Go
0x57	BIST_ERR_COUNT	BIST_ERR_COUNT	Go
0x58	BCC_CONFIG	BCC_CONFIG	Go
0x59	DATAPATH_CTL1	DATAPATH_CTL1	Go
0x5B	SER_ID	SER_ID	Go
0x5C	SER_ALIAS_ID	SER_ALIAS_ID	Go
0x5D	TARGET_ID_0	TARGET_ID_0	Go
0x5E	TARGET_ID_1	TARGET_ID_1	Go
0x5F	TARGET_ID_2	TARGET_ID_2	Go
0x60	TARGET_ID_3	TARGET_ID_3	Go
0x61	TARGET_ID_4	TARGET_ID_4	Go
0x62	TARGET_ID_5	TARGET_ID_5	Go
0x63	TARGET_ID_6	TARGET_ID_6	Go
0x64	TARGET_ID_7	TARGET_ID_7	Go
0x65	TARGET_ALIAS_0	TARGET_ALIAS_0	Go
0x66	TARGET_ALIAS_1	TARGET_ALIAS_1	Go
0x67	TARGET_ALIAS_2	TARGET_ALIAS_2	Go
0x68	TARGET_ALIAS_3	TARGET_ALIAS_3	Go
0x69	TARGET_ALIAS_4	TARGET_ALIAS_4	Go
0x6A	TARGET_ALIAS_5	TARGET_ALIAS_5	Go
0x6B	TARGET_ALIAS_6	TARGET_ALIAS_6	Go
0x6C	TARGET_ALIAS_7	TARGET_ALIAS_7	Go
0x6D	PORT_CONFIG	PORT_CONFIG	Go
0x6E	BC_GPIO_CTL0	BC_GPIO_CTL0	Go
0x6F	BC_GPIO_CTL1	BC_GPIO_CTL1	Go
0x70	RAW10_ID	RAW10_ID	Go
0x71	RAW12_ID	RAW12_ID	Go
0x72	CSI_VC_MAP	CSI_VC_MAP	Go
0x73	LINE_COUNT_1	LINE_COUNT_1	Go
0x74	LINE_COUNT_0	LINE_COUNT_0	Go
0x75	LINE_LEN_1	LINE_LEN_1	Go
0x76	LINE_LEN_0	LINE_LEN_0	Go
0x77	FREQ_DET_CTL	FREQ_DET_CTL	Go
0x78	MAILBOX_0	MAILBOX_0	Go
0x79	MAILBOX_1	MAILBOX_1	Go
0x7A	CSI_RX_STS	CSI_RX_STS	Go
0x7B	CSI_ERR_COUNTER	CSI_ERR_COUNTER	Go
0x7C	PORT_CONFIG2	PORT_CONFIG2	Go
0x7D	PORT_PASS_CTL	PORT_PASS_CTL	Go
0x7E	SEN_INT_RISE_CTL	SEN_INT_RISE_CTL	Go
0x7F	SEN_INT_FALL_CTL	SEN_INT_FALL_CTL	Go
0x90	CSI0_FRAME_COUNT_HI	CSI0_FRAME_COUNT_HI	Go
0x91	CSI0_FRAME_COUNT_LO	CSI0_FRAME_COUNT_LO	Go
0x92	CSI0_FRAME_ERR_COUNT_HI	CSI0_FRAME_ERR_COUNT_HI	Go
0x93	CSI0_FRAME_ERR_COUNT_LO	CSI0_FRAME_ERR_COUNT_LO	Go
0x94	CSI0_LINE_COUNT_HI	CSI0_LINE_COUNT_HI	Go
0x95	CSI0_LINE_COUNT_LO	CSI0_LINE_COUNT_LO	Go
0x96	CSI0_LINE_ERR_COUNT_HI	CSI0_LINE_ERR_COUNT_HI	Go
0x97	CSI0_LINE_ERR_COUNT_LO	CSI0_LINE_ERR_COUNT_LO	Go
0x98	CSI1_FRAME_COUNT_HI	CSI1_FRAME_COUNT_HI	Go
0x99	CSI1_FRAME_COUNT_LO	CSI1_FRAME_COUNT_LO	Go
0x9A	CSI1_FRAME_ERR_COUNT_HI	CSI1_FRAME_ERR_COUNT_HI	Go
0x9B	CSI1_FRAME_ERR_COUNT_LO	CSI1_FRAME_ERR_COUNT_LO	Go
0x9C	CSI1_LINE_COUNT_HI	CSI1_LINE_COUNT_HI	Go
0x9D	CSI1_LINE_COUNT_LO	CSI1_LINE_COUNT_LO	Go
0x9E	CSI1_LINE_ERR_COUNT_HI	CSI1_LINE_ERR_COUNT_HI	Go
0x9F	CSI1_LINE_ERR_COUNT_LO	CSI1_LINE_ERR_COUNT_LO	Go
0xA5	REFCLK_FREQ	REFCLK_FREQ	Go
0xB0	IND_ACC_CTL	IND_ACC_CTL	Go
0xB1	IND_ACC_ADDR	IND_ACC_ADDR	Go
0xB2	IND_ACC_DATA	IND_ACC_DATA	Go
0xB3	BIST_CTL	BIST_CTL	Go
0xB6	PAR_ERR_CTRL	PAR_ERR_CTRL	Go
0xB8	MODE_IDX_STS	MODE_IDX_STS	Go
0xB9	LINK_ERROR_COUNT	LINK_ERROR_COUNT	Go
0xBA	V3LINK_ENC_CTL	V3LINK_ENC_CTL	Go
0xBC	FV_MIN_TIME	FV_MIN_TIME	Go
0xBE	GPIO_PD_CTL	GPIO_PD_CTL	Go
0xD0	PORT_DEBUG	PORT_DEBUG	Go
0xD2	AEQ_CTL2	AEQ_CTL2	Go
0xD3	AEQ_STATUS	AEQ_STATUS	Go
0xD4	ADAPTIVE_EQ_BYPASS	ADAPTIVE_EQ_BYPASS	Go
0xD5	AEQ_MIN_MAX	AEQ_MIN_MAX	Go
0xD6	SFILTER_STS_0	SFILTER_STS_0	Go
0xD7	SFILTER_STS_1	SFILTER_STS_1	Go
0xD8	PORT_ICR_HI	PORT_ICR_HI	Go
0xD9	PORT_ICR_LO	PORT_ICR_LO	Go
0xDA	PORT_ISR_HI	PORT_ISR_HI	Go
0xDB	PORT_ISR_LO	PORT_ISR_LO	Go
0xDC	FC_GPIO_STS	FC_GPIO_STS	Go
0xDD	FC_GPIO_ICR	FC_GPIO_ICR	Go
0xDE	SEN_INT_RISE_STS	SEN_INT_RISE_STS	Go
0xDF	SEN_INT_FALL_STS	SEN_INT_FALL_STS	Go
0xF0	V3LINK_RX_ID0	V3LINK_RX_ID0	Go
0xF1	V3LINK_RX_ID1	V3LINK_RX_ID1	Go
0xF2	V3LINK_RX_ID2	V3LINK_RX_ID2	Go
0xF3	V3LINK_RX_ID3	V3LINK_RX_ID3	Go
0xF4	V3LINK_RX_ID4	V3LINK_RX_ID4	Go
0xF5	V3LINK_RX_ID5	V3LINK_RX_ID5	Go
0xF8	I2C_RX0_ID	I2C_RX0_ID	Go
0xF9	I2C_RX1_ID	I2C_RX1_ID	Go
0xFA	I2C_RX2_ID	I2C_RX2_ID	Go
0xFB	I2C_RX3_ID	I2C_RX3_ID	Go

Complex bit access types are encoded to fit into small table cells. Table 7-21 shows the codes that are used for access types in this section.

Table 7-21 Main Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
RC	R C	Read to Clear
RH	R H	Read Set or cleared by hardware
Write Type
W	W	Write
W1S	W 1S	Write 1 to set
WStrap	W Strap	Write Default value loaded from bootstrap pin after reset.
Reset or Default Value
-n		Value after reset or the default value

7.6.1.1 I2C_DEVICE_ID Register (Address = 0x0) [Reset = 0x00]

I2C_DEVICE_ID is shown in Table 7-22.

Return to the Summary Table.

The I2C Device ID Register field always indicates the current value of the I2C ID. When bit 0 of this register is 0, this field is read-only and shows the strapped ID from device initialization after power on. When bit 0 of this register is 1, this field is read/write and can be used to assign any valid I2C ID address to the deserializer.

Table 7-22 I2C_DEVICE_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	DEVICE_ID	R/WStrap	0x0	7-bit I2C ID of Deserializer (Strap) This field always indicates the current value of the I2C ID. When bit 0 of this register is 0, this field is read-only and show the strapped ID. When bit 1 of this register is 1, this field is read/write and can be used to assign any valid I2C ID. invalid
0	DES_ID	R/W	0x0	0: Device ID is from strap 1: Register I2C Device ID overrides strapped value

7.6.1.2 RESET_CTL Register (Address = 0x1) [Reset = 0x00]

RESET_CTL is shown in Table 7-23.

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The Reset Control register allows for soft digital reset of the TDES960 device internal circuitry without using PDB hardware analog reset. Digital Reset 0 is recommended if desired to reset without overwriting configuration registers to default values.

Table 7-23 RESET_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0x0	Reserved
5	RESERVED	R	0x0	Reserved
4:3	RESERVED	R	0x0	Reserved
2	RESTART_AUTOLOAD	RH/W1S	0x0	Restart ROM Auto-load Setting this bit to 1 causes a re-load of the ROM. This bit is self-clearing. Software may check for Auto-load complete by checking the CFG_INIT_DONE bit in the DEVICE_STS register.
1	DIGITAL_RESET1	RH/W1S	0x0	Digital Reset Resets the entire digital block including registers. This bit is self-clearing. 1: Reset 0: Normal operation
0	DIGITAL_RESET0	RH/W1S	0x0	Digital Reset Resets the entire digital block except registers. This bit is self-clearing. 1: Reset 0: Normal operation

7.6.1.3 GENERAL_CFG Register (Address = 0x2) [Reset = 0x1E]

GENERAL_CFG is shown in Table 7-24.

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The general configuration register enables and disables high level block functionality.

Table 7-24 GENERAL_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0x0	Reserved
5	I2C_CONTROLLER_EN	R/W	0x0	I2C Controller Enable When this bit is 0, the local I2C controller is disabled, when it is 1, the controller is enabled
4	OUTPUT_EN_MODE	R/W	0x1	Output Enable Mode If set to 0, the CSI-2 TX output port is forced to the high-impedance state if no assigned RX ports have an active Receiver lock. If set to 1, the CSI-2 TX output port will continue in normal operation if no assigned RX ports have an active Receiver lock. CSI-2 TX operation will remain under register control via the CSI_CTL register for each port. If no assigned RX ports have an active Receiver lock, this will result in the CSI-2 Transmitter entering the LP-11 state.
3	OUTPUT_ENABLE	R/W	0x1	Output Enable Control (in conjunction with Output Sleep State Select) If OUTPUT_SLEEP_STATE_SEL is set to 1 and this bit is set to 0, the CSI TX outputs will be forced into a high impedance state.
2	OUTPUT_SLEEP_STATE_SEL	R/W	0x1	OSS Select to control output state when LOCK is low (used in conjunction with Output Enable) When this bit is set to 0, the CSI TX outputs will be forced into a HS-0 state.
1	RX_PARITY_CHECK_EN	R/W	0x1	V3LINK Receiver Parity Checker Enable When enabled, the parity check function is enabled for the V3LINK receiver. This allows detection of errors on the V3LINK receiver data bits. 0: Disable 1: Enable
0	FORCE_REFCLK_DET	R/W	0x0	Force indication of external reference clock 0: Normal operation, reference clock detect circuit indicates the presence of an external reference clock 1: Force reference clock to be indicated present

7.6.1.4 REV_MASK_ID Register (Address = 0x3) [Reset = 0x40]

REV_MASK_ID is shown in Table 7-25.

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Revision ID field for production silicon version can be read back from this register.

Table 7-25 REV_MASK_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	REVISION_ID	R	0x4	Revision ID 0100: TDES960
3:0	MASK_ID	R	0x0	Mask ID

7.6.1.5 DEVICE_STS Register (Address = 0x4) [Reset = 0xC0]

DEVICE_STS is shown in Table 7-26.

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Device status register provides read back access to high level link diagnostics.

Table 7-26 DEVICE_STS Register Field Descriptions

Bit	Field	Type	Reset	Description
7	CFG_CKSUM_STS	R	0x1	Config Checksum Passed This bit is set following initialization if the Configuration data in the eFuse ROM had a valid checksum
6	CFG_INIT_DONE	R	0x1	Power-up initialization complete This bit is set after Initialization is complete. Configuration from eFuse ROM has completed.
5	RESERVED	R	0x0	Reserved
4	REFCLK_VALID	R	0x0	REFCLK valid frequency This bit indicates when a valid frequency has been detected on the REFCLK pin. 0: invalid frequency detected 1: REFCLK frequency between 12MHz and 64MHz
3:0	RESERVED	R	0x0	Reserved

7.6.1.6 PAR_ERR_THOLD_HI Register (Address = 0x5) [Reset = 0x01]

PAR_ERR_THOLD_HI is shown in Table 7-27.

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For each port, if the V3Link receiver detects a number of parity errors greater than or equal to total value in PAR_ERR_THOLD[15:0], the PARITY_ERROR flag is set in the RX_PORT_STS1 register. PAR_ERR_THOLD_HI contains bits [15:8] of the 16 bit parity error threshold PAR_ERR_THOLD[15:0].

Table 7-27 PAR_ERR_THOLD_HI Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PAR_ERR_THOLD_HI	R/W	0x1	V3LINK Parity Error Threshold High byte This register provides the 8 most significant bits of the Parity Error Threshold value. For each port, if the V3Link receiver detects a number of parity errors greater than or equal to this value, the PARITY_ERROR flag is set in the RX_PORT_STS1 register.

7.6.1.7 PAR_ERR_THOLD_LO Register (Address = 0x6) [Reset = 0x00]

PAR_ERR_THOLD_LO is shown in Table 7-28.

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For each port, if the V3Link receiver detects a number of parity errors greater than or equal to total value in PAR_ERR_THOLD[15:0], the PARITY_ERROR flag is set in the RX_PORT_STS1 register. PAR_ERR_THOLD_LO contains bits [7:0] of the 16-bit parity error threshold PAR_ERR_THOLD[15:0].

Table 7-28 PAR_ERR_THOLD_LO Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PAR_ERR_THOLD_LO	R/W	0x0	V3LINK Parity Error Threshold Low byte This register provides the 8 least significant bits of the Parity Error Threshold value. For each port, if the V3Link receiver detects a number of parity errors greater than or equal to this value, the PARITY_ERROR flag is set in the RX_PORT_STS1 register.

7.6.1.8 BCC_WATCHDOG_CONTROL Register (Address = 0x7) [Reset = 0xFE]

BCC_WATCHDOG_CONTROL is shown in Table 7-29.

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The BCC watchdog timer allows termination of a control channel transaction if it fails to complete within a programmed amount of time.

Table 7-29 BCC_WATCHDOG_CONTROL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	BCC_WATCHDOG_TIMER_	R/W	0x7F	The watchdog timer allows termination of a control channel transaction if it fails to complete within a programmed amount of time. This field sets the Bi-directional Control Channel Watchdog Timeout value in units of 2 milliseconds. This field must not be set to 0.
0	BCC_WATCHDOG_TIMER_DISABLE	R/W	0x0	Disable Bi-directional Control Channel Watchdog Timer 1: Disables BCC Watchdog Timer operation 0: Enables BCC Watchdog Timer operation

7.6.1.9 I2C_CONTROL_1 Register (Address = 0x8) [Reset = 0x1C]

I2C_CONTROL_1 is shown in Table 7-30.

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Table 7-30 I2C_CONTROL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	LOCAL_WRITE_DISABLE	R/W	0x0	Disable Remote Writes to Local Registers Setting this bit to a 1 will prevent remote writes to local device registers from across the control channel. This prevents writes to the Deserializer registers from an I2C controller attached to the Serializer. Setting this bit does not affect remote access to I2C targets at the Deserializer.
6:4	I2C_SDA_HOLD	R/W	0x1	Internal SDA Hold Time This field configures the amount of internal hold time provided for the SDA input relative to the SCL input. Units are 50 nanoseconds.
3:0	I2C_FILTER_DEPTH	R/W	0xC	I2C Glitch Filter Depth This field configures the maximum width of glitch pulses on the SCL and SDA inputs that is rejected. Units are 5 nanoseconds.

7.6.1.10 I2C_CONTROL_2 Register (Address = 0x9) [Reset = 0x12]

I2C_CONTROL_2 is shown in Table 7-31.

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Table 7-31 I2C_CONTROL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	SDA_OUTPUT_SETUP	R/W	0x1	Remote Ack SDA Output Setup When a Control Channel (remote) access is active, this field configures setup time from the SDA output relative to the rising edge of SCL during ACK cycles. Setting this value will increase setup time in units of 640ns. The nominal output setup time value for SDA to SCL when this field is 0 is 80ns.
3:2	SDA_OUTPUT_DELAY	R/W	0x0	SDA Output Delay This field configures additional delay on the SDA output relative to the falling edge of SCL. Setting this value will increase output delay in units of 40ns. Nominal output delay values for SCL to SDA are: 00: 240ns 01: 280ns 10: 320ns 11: 360ns
1	I2C_BUS_TIMER_SPEEDUP	R/W	0x1	Speed up I2C Bus Watchdog Timer 1: Watchdog Timer expires after approximately 50 microseconds 0: Watchdog Timer expires after approximately 1 second.
0	I2C_BUS_TIMER_DISABLE	R/W	0x0	Disable I2C Bus Watchdog Timer When the I2C Watchdog Timer may be used to detect when the I2C bus is free or hung up following an invalid termination of a transaction. If SDA is high and no signaling occurs for approximately 1 second, the I2C bus will assumed to be free. If SDA is low and no signaling occurs, the device will attempt to clear the bus by driving 9 clocks on SCL

7.6.1.11 SCL_HIGH_TIME Register (Address = 0xA) [Reset = 0x7A]

SCL_HIGH_TIME is shown in Table 7-32.

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The SCL High Time register field configures the high pulse width of the I2C SCL output when the Serializer is the Controller on the local I2C bus. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to approximately 100 kHz with the internal oscillator clock running at nominal 25 MHz. Delay includes 4 additional oscillator clock periods. The internal oscillator has ±10% variation when REFCLK is not applied, which must be taken into account when setting the SCL High and Low Time registers.

Table 7-32 SCL_HIGH_TIME Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	SCL_HIGH_TIME	R/W	0x7A	I2C Controller SCL High Time This field configures the high pulse width of the SCL output when the Serializer is the Controller on the local I2C bus. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5us SCL high time with the reference clock at 25 MHz + 100ppm. The delay includes 5 additional oscillator clock periods. Min_delay= 39.996ns * (SCL_HIGH_TIME + 5)

7.6.1.12 SCL_LOW_TIME Register (Address = 0xB) [Reset = 0x7A]

SCL_LOW_TIME is shown in Table 7-33.

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The SCL Low Time register field configures the low pulse width of the SCL output when the serializer is the controller on the local I2C bus. This value is also used as the SDA setup time by the I2C Target for providing data prior to releasing SCL during accesses over the Bidirectional control channel. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to approximately 100 kHz with the internal oscillator clock running at nominal 25 MHz. Delay includes 4 additional oscillator clock periods. The internal oscillator has ±10% variation when REFCLK is not applied, which must be taken into account when setting the SCL High and Low Time registers

Table 7-33 SCL_LOW_TIME Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	SCL_LOW_TIME	R/W	0x7A	I2C SCL Low Time This field configures the low pulse width of the SCL output when the Serializer is the Controller on the local I2C bus. This value is also used as the SDA setup time by the I2C Target for providing data prior to releasing SCL during accesses over the Bi-directional Control Channel. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5us SCL low time with the reference clock at 25 MHz + 100ppm. The delay includes 5 additional clock periods. Min_delay= 39.996ns * (SCL_LOW_TIME+ 5)

7.6.1.13 RX_PORT_CTL Register (Address = 0xC) [Reset = 0x0F]

RX_PORT_CTL is shown in Table 7-34.

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Receiver port control register assigns rules for lock and pass in the general status register and allows for enabling and disabling each Rx port.

Table 7-34 RX_PORT_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BCC3_MAP	R/W	0x0	Map Control Channel 3 to I2C Target Port 0: I2C Target Port 0 1: I2C Target Port 1
6	BCC2_MAP	R/W	0x0	Map Control Channel 2 to I2C Target Port 0: I2C Target Port 0 1: I2C Target Port 1
5	BCC1_MAP	R/W	0x0	Map Control Channel 1 to I2C Target Port 0: I2C Target Port 0 1: I2C Target Port 1
4	BCC0_MAP	R/W	0x0	Map Control Channel 0 to I2C Target Port 0: I2C Target Port 0 1: I2C Target Port 1
3	PORT3_EN	R/W	0x1	Port 3 Receiver Enable 0: Disable Port 3 Receiver 1: Enable Port 3 Receiver
2	PORT2_EN	R/W	0x1	Port 2 Receiver Enable 0: Disable Port 2 Receiver 1: Enable Port 2 Receiver
1	PORT1_EN	R/W	0x1	Port 1 Receiver Enable 0: Disable Port 1 Receiver 1: Enable Port 1 Receiver
0	PORT0_EN	R/W	0x1	Port 0 Receiver Enable 0: Disable Port 0 Receiver 1: Enable Port 0 Receiver

7.6.1.14 IO_CTL Register (Address = 0xD) [Reset = 0x09]

IO_CTL is shown in Table 7-35.

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Table 7-35 IO_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SEL3P3V	R/W	0x0	3.3V I/O Select on pins INTB, I2C, GPIO 0: 1.8V I/O Supply 1: 3.3V I/O Supply If IO_SUPPLY_MODE_OV is 0, a read of this register will return the detected I/O voltage level.
6	IO_SUPPLY_MODE_OV	R/W	0x0	Override I/O Supply Mode bit If set to 0, the detected voltage level is used for both SEL3P3V and IO_SUPPLY_MODE controls. If set to 1, the values written to the SEL3P3V and IO_SUPPLY_MODE fields is used.
5:4	IO_SUPPLY_MODE	R/W	0x0	I/O Supply Mode 00: 1.8V 11: 3.3V If IO_SUPPLY_MODE_OV is 0, a read of this register will return the detected I/O voltage level.
3:0	RESERVED	R	0x0	Reserved

7.6.1.15 GPIO_PIN_STS Register (Address = 0xE) [Reset = 0x00]

GPIO_PIN_STS is shown in Table 7-36.

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This register reads the current values on each of the 8 GPIO pins.

Table 7-36 GPIO_PIN_STS Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	GPIO_STS	R	0x0	GPIO Pin Status This register reads the current values on each of the 8 GPIO pins. Bit 7 reads GPIO7 and bit 0 reads GPIO0.

7.6.1.16 GPIO_INPUT_CTL Register (Address = 0xF) [Reset = 0xFF]

GPIO_INPUT_CTL is shown in Table 7-37.

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Table 7-37 GPIO_INPUT_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	GPIO7_INPUT_EN	R/W	0x1	GPIO7 Input Enable 0: Disabled 1: Enabled
6	GPIO6_INPUT_EN	R/W	0x1	GPIO6 Input Enable 0: Disabled 1: Enabled
5	GPIO5_INPUT_EN	R/W	0x1	GPIO5 Input Enable 0: Disabled 1: Enabled
4	GPIO4_INPUT_EN	R/W	0x1	GPIO4 Input Enable 0: Disabled 1: Enabled
3	GPIO3_INPUT_EN	R/W	0x1	GPIO3 Input Enable 0: Disabled 1: Enabled
2	GPIO2_INPUT_EN	R/W	0x1	GPIO2 Input Enable 0: Disabled 1: Enabled
1	GPIO1_INPUT_EN	R/W	0x1	GPIO1 Input Enable 0: Disabled 1: Enabled
0	GPIO0_INPUT_EN	R/W	0x1	GPIO0 Input Enable 0: Disabled 1: Enabled

7.6.1.17 GPIO0_PIN_CTL Register (Address = 0x10) [Reset = 0x00]

GPIO0_PIN_CTL is shown in Table 7-38.

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Table 7-38 GPIO0_PIN_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	GPIO0_OUT_SEL	R/W	0x0	GPIO0 Output Select Determines the output data for the selected source. If GPIO0_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000: Received GPIO0 001: Received GPIO1 010: Received GPIO2 011: Received GPIO3 100: RX Port Lock indication 101: RX Port Pass indication 110: Frame Valid signal 111: Line Valid signal If GPIO0_OUT_SRC is set to 100 (Device Status), the following selections apply: 000: Value in GPIO0_OUT_VAL 001: Logical OR of Lock indication from enabled RX ports 010: Logical AND of Lock indication from enabled RX ports 011: Logical AND of Pass indication from enabled RX ports 100: FrameSync signal 101 - 111: Reserved If GPIO0_OUT_SRC is set to 11x (one of the CSI-2 Transmit ports), the following selections apply: 000: Pass (AND of selected RX port status) 001: Pass (OR of selected RX port status) 010: Frame Valid (sending video frame) 011: Line Valid (sending video line) 100: Synchronized - multi-port data is synchronized 101: CSI-2 TX Port Interrupt 111: Reserved
4:2	GPIO0_OUT_SRC	R/W	0x0	GPIO0 Output Source Select Selects output source for GPIO0 data: 000: RX Port 0 001: RX Port 1 010: RX Port 2 011: RX Port 3 100: Device Status 101: Reserved 110: CSI-2 TX Port 0 111: CSI-2 TX Port 1
1	GPIO0_OUT_VAL	R/W	0x0	GPIO0 Output Value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value.
0	GPIO0_OUT_EN	R/W	0x0	GPIO0 Output Enable 0: Disabled 1: Enabled

7.6.1.18 GPIO1_PIN_CTL Register (Address = 0x11) [Reset = 0x00]

GPIO1_PIN_CTL is shown in Table 7-39.

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Table 7-39 GPIO1_PIN_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	GPIO1_OUT_SEL	R/W	0x0	GPIO1 Output Select Determines the output data for the selected source. If GPIO1_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000: Received GPIO0 001: Received GPIO1 010: Received GPIO2 011: Received GPIO3 100: RX Port Lock indication 101: RX Port Pass indication 110: Frame Valid signal 111: Line Valid signal If GPIO1_OUT_SRC is set to 100 (Device Status), the following selections apply: 000: Value in GPIO1_OUT_VAL 001: Logical OR of Lock indication from enabled RX ports 010: Logical AND of Lock indication from enabled RX ports 011: Logical AND of Pass indication from enabled RX ports 100: FrameSync signal 101 - 111: Reserved If GPIO1_OUT_SRC is set to 11x (one of the CSI-2 Transmit ports), the following selections apply: 000: Pass (AND of selected RX port status) 001: Pass (OR of selected RX port status) 010: Frame Valid (sending video frame) 011: Line Valid (sending video line) 100: Synchronized - multi-port data is synchronized 101: CSI-2 TX Port Interrupt 111: Reserved
4:2	GPIO1_OUT_SRC	R/W	0x0	GPIO1 Output Source Select Selects output source for GPIO1 data: 000: RX Port 0 001: RX Port 1 010: RX Port 2 011: RX Port 3 100: Device Status 101: Reserved 110: CSI-2 TX Port 0 111: CSI-2 TX Port 1
1	GPIO1_OUT_VAL	R/W	0x0	GPIO1 Output Value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value.
0	GPIO1_OUT_EN	R/W	0x0	GPIO1 Output Enable 0: Disabled 1: Enabled

7.6.1.19 GPIO2_PIN_CTL Register (Address = 0x12) [Reset = 0x00]

GPIO2_PIN_CTL is shown in Table 7-40.

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Table 7-40 GPIO2_PIN_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	GPIO2_OUT_SEL	R/W	0x0	GPIO2 Output Select Determines the output data for the selected source. If GPIO2_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000: Received GPIO0 001: Received GPIO1 010: Received GPIO2 011: Received GPIO3 100: RX Port Lock indication 101: RX Port Pass indication 110: Frame Valid signal 111: Line Valid signal If GPIO2_OUT_SRC is set to 100 (Device Status), the following selections apply: 000: Value in GPIO2_OUT_VAL 001: Logical OR of Lock indication from enabled RX ports 010: Logical AND of Lock indication from enabled RX ports 011: Logical AND of Pass indication from enabled RX ports 100: FrameSync signal 101 - 111: Reserved If GPIO2_OUT_SRC is set to 11x (one of the CSI-2 Transmit ports), the following selections apply: 000: Pass (AND of selected RX port status) 001: Pass (OR of selected RX port status) 010: Frame Valid (sending video frame) 011: Line Valid (sending video line) 100: Synchronized - multi-port data is synchronized 101: CSI-2 TX Port Interrupt 111: Reserved
4:2	GPIO2_OUT_SRC	R/W	0x0	GPIO2 Output Source Select Selects output source for GPIO2 data: 000: RX Port 0 001: RX Port 1 010: RX Port 2 011: RX Port 3 100: Device Status 101: Reserved 110: CSI-2 TX Port 0 111: CSI-2 TX Port 1
1	GPIO2_OUT_VAL	R/W	0x0	GPIO2 Output Value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value.
0	GPIO2_OUT_EN	R/W	0x0	GPIO2 Output Enable 0: Disabled 1: Enabled

7.6.1.20 GPIO3_PIN_CTL Register (Address = 0x13) [Reset = 0x00]

GPIO3_PIN_CTL is shown in Table 7-41.

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Table 7-41 GPIO3_PIN_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	GPIO3_OUT_SEL	R/W	0x0	GPIO3 Output Select Determines the output data for the selected source. If GPIO3_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000: Received GPIO0 001: Received GPIO1 010: Received GPIO2 011: Received GPIO3 100: RX Port Lock indication 101: RX Port Pass indication 110: Frame Valid signal 111: Line Valid signal If GPIO3_OUT_SRC is set to 100 (Device Status), the following selections apply: 000: Value in GPIO3_OUT_VAL 001: Logical OR of Lock indication from enabled RX ports 010: Logical AND of Lock indication from enabled RX ports 011: Logical AND of Pass indication from enabled RX ports 100: FrameSync signal 101 - 111: Reserved If GPIO3_OUT_SRC is set to 11x (one of the CSI-2 Transmit ports), the following selections apply: 000: Pass (AND of selected RX port status) 001: Pass (OR of selected RX port status) 010: Frame Valid (sending video frame) 011: Line Valid (sending video line) 100: Synchronized - multi-port data is synchronized 101: CSI-2 TX Port Interrupt 111: Reserved
4:2	GPIO3_OUT_SRC	R/W	0x0	GPIO3 Output Source Select Selects output source for GPIO3 data: 000: RX Port 0 001: RX Port 1 010: RX Port 2 011: RX Port 3 100: Device Status 101: Reserved 110: CSI-2 TX Port 0 111: CSI-2 TX Port 1
1	GPIO3_OUT_VAL	R/W	0x0	GPIO3 Output Value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value.
0	GPIO3_OUT_EN	R/W	0x0	GPIO3 Output Enable 0: Disabled 1: Enabled

7.6.1.21 GPIO4_PIN_CTL Register (Address = 0x14) [Reset = 0x00]

GPIO4_PIN_CTL is shown in Table 7-42.

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Table 7-42 GPIO4_PIN_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	GPIO4_OUT_SEL	R/W	0x0	GPIO4 Output Select Determines the output data for the selected source. If GPIO4_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000: Received GPIO0 001: Received GPIO1 010: Received GPIO2 011: Received GPIO3 100: RX Port Lock indication 101: RX Port Pass indication 110: Frame Valid signal 111: Line Valid signal If GPIO4_OUT_SRC is set to 100 (Device Status), the following selections apply: 000: Value in GPIO4_OUT_VAL 001: Logical OR of Lock indication from enabled RX ports 010: Logical AND of Lock indication from enabled RX ports 011: Logical AND of Pass indication from enabled RX ports 100: FrameSync signal 101 - 111: Reserved If GPIO4_OUT_SRC is set to 11x (one of the CSI-2 Transmit ports), the following selections apply: 000: Pass (AND of selected RX port status) 001: Pass (OR of selected RX port status) 010: Frame Valid (sending video frame) 011: Line Valid (sending video line) 100: Synchronized - multi-port data is synchronized 101: CSI-2 TX Port Interrupt 111: Reserved
4:2	GPIO4_OUT_SRC	R/W	0x0	GPIO4 Output Source Select Selects output source for GPIO4 data: 000: RX Port 0 001: RX Port 1 010: RX Port 2 011: RX Port 3 100: Device Status 101: Reserved 110: CSI-2 TX Port 0 111: CSI-2 TX Port 1
1	GPIO4_OUT_VAL	R/W	0x0	GPIO4 Output Value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value.
0	GPIO4_OUT_EN	R/W	0x0	GPIO4 Output Enable 0: Disabled 1: Enabled

7.6.1.22 GPIO5_PIN_CTL Register (Address = 0x15) [Reset = 0x00]

GPIO5_PIN_CTL is shown in Table 7-43.

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Table 7-43 GPIO5_PIN_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	GPIO5_OUT_SEL	R/W	0x0	GPIO5 Output Select Determines the output data for the selected source. If GPIO5_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000: Received GPIO0 001: Received GPIO1 010: Received GPIO2 011: Received GPIO3 100: RX Port Lock indication 101: RX Port Pass indication 110: Frame Valid signal 111: Line Valid signal If GPIO5_OUT_SRC is set to 100 (Device Status), the following selections apply: 000: Value in GPIO5_OUT_VAL 001: Logical OR of Lock indication from enabled RX ports 010: Logical AND of Lock indication from enabled RX ports 011: Logical AND of Pass indication from enabled RX ports 100: FrameSync signal 101 - 111: Reserved If GPIO5_OUT_SRC is set to 11x (one of the CSI-2 Transmit ports), the following selections apply: 000: Pass (AND of selected RX port status) 001: Pass (OR of selected RX port status) 010: Frame Valid (sending video frame) 011: Line Valid (sending video line) 100: Synchronized - multi-port data is synchronized 101: CSI-2 TX Port Interrupt 111: Reserved
4:2	GPIO5_OUT_SRC	R/W	0x0	GPIO5 Output Source Select Selects output source for GPIO5 data: 000: RX Port 0 001: RX Port 1 010: RX Port 2 011: RX Port 3 100: Device Status 101: Reserved 110: CSI-2 TX Port 0 111: CSI-2 TX Port 1
1	GPIO5_OUT_VAL	R/W	0x0	GPIO5 Output Value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value.
0	GPIO5_OUT_EN	R/W	0x0	GPIO5 Output Enable 0: Disabled 1: Enabled

7.6.1.23 GPIO6_PIN_CTL Register (Address = 0x16) [Reset = 0x00]

GPIO6_PIN_CTL is shown in Table 7-44.

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Table 7-44 GPIO6_PIN_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	GPIO6_OUT_SEL	R/W	0x0	GPIO6 Output Select Determines the output data for the selected source. If GPIO6_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000: Received GPIO0 001: Received GPIO1 010: Received GPIO2 011: Received GPIO3 100: RX Port Lock indication 101: RX Port Pass indication 110: Frame Valid signal 111: Line Valid signal If GPIO6_OUT_SRC is set to 100 (Device Status), the following selections apply: 000: Value in GPIO6_OUT_VAL 001: Logical OR of Lock indication from enabled RX ports 010: Logical AND of Lock indication from enabled RX ports 011: Logical AND of Pass indication from enabled RX ports 100: FrameSync signal 101 - 111: Reserved If GPIO6_OUT_SRC is set to 11x (one of the CSI-2 Transmit ports), the following selections appy: 000: Pass (AND of selected RX port status) 001: Pass (OR of selected RX port status) 010: Frame Valid (sending video frame) 011: Line Valid (sending video line) 100: Synchronized - multi-port data is synchronized 101: CSI-2 TX Port Interrupt 111: Reserved
4:2	GPIO6_OUT_SRC	R/W	0x0	GPIO6 Output Source Select Selects output source for GPIO6 data: 000: RX Port 0 001: RX Port 1 010: RX Port 2 011: RX Port 3 100: Device Status 101: Reserved 110: CSI-2 TX Port 0 111: CSI-2 TX Port 1
1	GPIO6_OUT_VAL	R/W	0x0	GPIO6 Output Value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value.
0	GPIO6_OUT_EN	R/W	0x0	GPIO6 Output Enable 0: Disabled 1: Enabled

7.6.1.24 GPIO7_PIN_CTL Register (Address = 0x17) [Reset = 0x00]

GPIO7_PIN_CTL is shown in Table 7-45.

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Table 7-45 GPIO7_PIN_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	GPIO7_OUT_SEL	R/W	0x0	GPIO7 Output Select Determines the output data for the selected source. If GPIO7_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000: Received GPIO0 001: Received GPIO1 010: Received GPIO2 011: Received GPIO3 100: RX Port Lock indication 101: RX Port Pass indication 110: Frame Valid signal 111: Line Valid signal If GPIO7_OUT_SRC is set to 100 (Device Status), the following selections apply: 000: Value in GPIO7_OUT_VAL 001: Logical OR of Lock indication from enabled RX ports 010: Logical AND of Lock indication from enabled RX ports 011: Logical AND of Pass indication from enabled RX ports 100: FrameSync signal 101 - 111: Reserved If GPIO7_OUT_SRC is set to 11x (one of the CSI-2 Transmit ports), the following selections apply: 000: Pass (AND of selected RX port status) 001: Pass (OR of selected RX port status) 010: Frame Valid (sending video frame) 011: Line Valid (sending video line) 100: Synchronized - multi-port data is synchronized 101: CSI-2 TX Port Interrupt 111: Reserved
4:2	GPIO7_OUT_SRC	R/W	0x0	GPIO7 Output Source Select Selects output source for GPIO7 data: 000: RX Port 0 001: RX Port 1 010: RX Port 2 011: RX Port 3 100: Device Status 101: Reserved 110: CSI-2 TX Port 0 111: CSI-2 TX Port 1
1	GPIO7_OUT_VAL	R/W	0x0	GPIO7 Output Value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value.
0	GPIO7_OUT_EN	R/W	0x0	GPIO7 Output Enable 0: Disabled 1: Enabled

7.6.1.25 FS_CTL Register (Address = 0x18) [Reset = 0x00]

FS_CTL is shown in Table 7-46.

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Table 7-46 FS_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	FS_MODE	R/W	0x0	FrameSync Mode 0000: Internal Generated FrameSync, use Back-channel frame clock from port 0 0001: Internal Generated FrameSync, use Back-channel frame clock from port 1 0010: Internal Generated FrameSync, use Back-channel frame clock from port 2 0011: Internal Generated FrameSync, use Back-channel frame clock from port 3 01xx: Internal Generated FrameSync, use 25MHz clock 1000: External FrameSync from GPIO0 1001: External FrameSync from GPIO1 1010: External FrameSync from GPIO2 1011: External FrameSync from GPIO3 1100: External FrameSync from GPIO4 1101: External FrameSync from GPIO5 1110: External FrameSync from GPIO6 1111: External FrameSync from GPIO7
3	FS_SINGLE	RH/W1S	0x0	Generate Single FrameSync pulse When this bit is set, a single FrameSync pulse is generated. The system should wait for the full duration of the desired pulse before generating another pulse. When using this feature, the FS_GEN_ENABLE bit should remain set to 0. This bit is self-clearing and will always return 0.
2	FS_INIT_STATE	R/W	0x0	Initial State This register controls the initial state of the FrameSync signal. 0: FrameSync initial state is 0 1: FrameSync initial state is 1
1	FS_GEN_MODE	R/W	0x0	FrameSync Generation Mode This control selects between Hi/Lo and 50/50 modes. In Hi/Lo mode, the FrameSync generator will use the FS_HIGH_TIME[15:0] and FS_LOW_TIME[15:0] register values to separately control the High and Low periods for the generated FrameSync signal. In 50/50 mode, the FrameSync generator will use the values in the FS_HIGH_TIME_0, FS_LOW_TIME_1 and FS_LOW_TIME_0 registers as a 24-bit value for both the High and Low periods of the generated FrameSync signal. 0: Hi/Lo 1: 50/50
0	FS_GEN_ENABLE	R/W	0x0	FrameSync Generation Enable 0: Disabled 1: Enabled

7.6.1.26 FS_HIGH_TIME_1 Register (Address = 0x19) [Reset = 0x00]

FS_HIGH_TIME_1 is shown in Table 7-47.

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Table 7-47 FS_HIGH_TIME_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	FRAMESYNC_HIGH_TIME_1	R/W	0x0	FrameSync High Time bits 15:8 The value programmed to the FS_HIGH_TIME register should be reduced by 1 from the desired delay. For example, a value of 0 in the FRAMESYNC_HIGH_TIME field will result in a 1 cycle high pulse on the FrameSync signal.

7.6.1.27 FS_HIGH_TIME_0 Register (Address = 0x1A) [Reset = 0x00]

FS_HIGH_TIME_0 is shown in Table 7-48.

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Table 7-48 FS_HIGH_TIME_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	FRAMESYNC_HIGH_TIME_0	R/W	0x0	FrameSync High Time bits 7:0 The value programmed to the FS_HIGH_TIME register should be reduced by 1 from the desired delay. For example, a value of 0 in the FRAMESYNC_HIGH_TIME field will result in a 1 cycle high pulse on the FrameSync signal.

7.6.1.28 FS_LOW_TIME_1 Register (Address = 0x1B) [Reset = 0x00]

FS_LOW_TIME_1 is shown in Table 7-49.

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Table 7-49 FS_LOW_TIME_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	FRAMESYNC_LOW_TIME_1	R/W	0x0	FrameSync Low Time bits 15:8 The value programmed to the FS_LOW_TIME register should be reduced by 1 from the desired delay. For example, a value of 0 in the FRAMESYNC_LOW_TIME field will result in a 1 cycle high pulse on the FrameSync signal.

7.6.1.29 FS_LOW_TIME_0 Register (Address = 0x1C) [Reset = 0x00]

FS_LOW_TIME_0 is shown in Table 7-50.

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Table 7-50 FS_LOW_TIME_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	FRAMESYNC_LOW_TIME_0	R/W	0x0	FrameSync Low Time bits 7:0 The value programmed to the FS_LOW_TIME register should be reduced by 1 from the desired delay. For example, a value of 0 in the FRAMESYNC_LOW_TIME field will result in a 1 cycle high pulse on the FrameSync signal.

7.6.1.30 MAX_FRM_HI Register (Address = 0x1D) [Reset = 0x00]

MAX_FRM_HI is shown in Table 7-51.

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Table 7-51 MAX_FRM_HI Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	MAX_FRAME_HI	R/W	0x0	CSI-2 Maximum Frame Count bits 15:8 In RAW mode operation, the V3LINK Receiver will create CSI-2 video frames. For the Frame Start and Frame End packets of each video frame, a 16-bit frame number field is generated. If the Maximum Frame Count value is set to 0, the frame number is disabled and will always be 0. If Maximum Frame Count value is non-zero, the frame number will increment for each from 1 up to the Maximum Frame Count value before resetting to 1.

7.6.1.31 MAX_FRM_LO Register (Address = 0x1E) [Reset = 0x04]

MAX_FRM_LO is shown in Table 7-52.

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Table 7-52 MAX_FRM_LO Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	MAX_FRAME_LO	R/W	0x4	CSI-2 Maximum Frame Count bits 7:0 In RAW mode operation, the V3LINK Receiver will create CSI-2 video frames. For the Frame Start and Frame End packets of each video frame, a 16-bit frame number field is generated. If the Maximum Frame Count value is set to 0, the frame number is disabled and will always be 0. If Maximum Frame Count value is non-zero, the frame number will increment for each from 1 up to the Maximum Frame Count value before resetting to 1.

7.6.1.32 CSI_PLL_CTL Register (Address = 0x1F) [Reset = 0x02]

CSI_PLL_CTL is shown in Table 7-53.

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Table 7-53 CSI_PLL_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0x0	Reserved
3	SEL_OSC_200M	R/W	0x0	Select 200MHz Oscillator Clock The external reference clock is normally used to generate the digital and CSI-2 PLL reference clocks. This bit allows the use of the internal 200 MHz always-on oscillator clock instead. 0: Select external reference clock 1: Select internal always-on clock
2	REF_CLK_MODE	R/W	0x0	Reference Clock mode The digital logic requires a 200 MHz reference clock generated from the CSI-2 PLL. If this bit is set to 1, the reference clock will be 100 MHz. 0: clock is 200 MHz 1: clock is 100 MHz This bit should not be set to 1 if CSI_TX_SPEED is set for 400Mbps operation.
1:0	CSI_TX_SPEED	R/W	0x2	CSI-2 Transmitter Speed select: Controls the CSI-2 Transmitter frequency. 00: 1.472 - 1.664 Gbps serial rate 01: 1.2 Gbps serial rate 10: 800 Mbps serial rate 11: 400 Mbps serial rate

7.6.1.33 FWD_CTL1 Register (Address = 0x20) [Reset = 0xF0]

FWD_CTL1 is shown in Table 7-54.

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Table 7-54 FWD_CTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	FWD_PORT3_DIS	R/W	0x1	Disable forwarding of RX Port 3 0: Forwarding enabled 1: Forwarding disabled
6	FWD_PORT2_DIS	R/W	0x1	Disable forwarding of RX Port 2 0: Forwarding enabled 1: Forwarding disabled
5	FWD_PORT1_DIS	R/W	0x1	Disable forwarding of RX Port 1 0: Forwarding enabled 1: Forwarding disabled
4	FWD_PORT0_DIS	R/W	0x1	Disable forwarding of RX Port 0 0: Forwarding enabled 1: Forwarding disabled
3	RX3_MAP	R/W	0x0	Map RX Port 3 to CSI-2 Port 0: CSI-2 Port 0 1: CSI-2 Port 1 It is recommended to disable forwarding for a port before changing the port mapping.
2	RX2_MAP	R/W	0x0	Map RX Port 2 to CSI-2 Port 0: CSI-2 Port 0 1: CSI-2 Port 1 It is recommended to disable forwarding for a port before changing the port mapping.
1	RX1_MAP	R/W	0x0	Map RX Port 1 to CSI-2 Port 0: CSI-2 Port 0 1: CSI-2 Port 1 It is recommended to disable forwarding for a port before changing the port mapping.
0	RX0_MAP	R/W	0x0	Map RX Port 0 to CSI-2 Port 0: CSI-2 Port 0 1: CSI-2 Port 1 It is recommended to disable forwarding for a port before changing the port mapping.

7.6.1.34 FWD_CTL2 Register (Address = 0x21) [Reset = 0x03]

FWD_CTL2 is shown in Table 7-55.

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Table 7-55 FWD_CTL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	CSI_REPLICATE	R/W	0x0	CSI-2 Replicate Mode When set to a 1, the CSI-2 output from port 0 will also be generated on CSI-2 port 1. The same output data is presented on both ports.
6	FWD_SYNC_AS_AVAIL	R/W	0x0	Synchronized Forwarding As Available During Synchronized Forwarding, each forwarding engine will wait for video data to be available from each enabled port, prior to sending the video line. Setting this bit to a 1 will allow sending the next video line as it becomes available. For example if RX Ports 0 and 1 are being forwarded, port 0 video line will be forwarded when it becomes available, rather than waiting until both ports 0 and ports 1 have video data available. This operation may reduce the likelihood of buffer overflow errors in some conditions. This bit will have no affect in video line concatenation mode and only affects video lines (long packets) rather than synchronization packets. This bit applies to both CSI-2 output ports
5:4	CSI1_SYNC_FWD	R/W	0x0	Enable synchronized forwarding for CSI-2 output port 1 00: Synchronized forwarding disabled 01: Basic Synchronized forwarding enabled 10: Synchronous forwarding with line interleaving 11: Synchronous forwarding with line concatenation Only one of CSI1_RR_FWD and CSI1_SYNC_FWD must be enabled at a time.
3:2	CSI0_SYNC_FWD	R/W	0x0	Enable synchronized forwarding for CSI-2 output port 0 00: Synchronized forwarding disabled 01: Basic Synchronized forwarding enabled 10: Synchronous forwarding with line interleaving 11: Synchronous forwarding with line concatenation Only one of CSI0_RR_FWD and CSI0_SYNC_FWD must be enabled at a time.
1	CSI1_RR_FWD	R/W	0x1	Enable best-effort forwarding for CSI-2 output port 1. When this mode is enabled, no attempt is made to synchronize the video traffic. When multiple sources have data available to forward, the data will tend to be forwarded in a round-robin fashion. 0: Round robin forwarding disabled 1: Round robin forwarding enabled Only one of CSI1_RR_FWD and CSI1_SYNC_FWD must be enabled at a time.
0	CSI0_RR_FWD	R/W	0x1	Enable best-effort forwarding for CSI-2 output port 0. When this mode is enabled, no attempt is made to synchronize the video traffic. When multiple sources have data available to forward, the data will tend to be forwarded in a round-robin fashion. 0: Round robin forwarding disabled 1: Round robin forwarding enabled Only one of CSI0_RR_FWD and CSI0_SYNC_FWD must be enabled at a time.

7.6.1.35 FWD_STS Register (Address = 0x22) [Reset = 0x00]

FWD_STS is shown in Table 7-56.

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Table 7-56 FWD_STS Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0x0	Reserved
3	FWD_SYNC_FAIL1	RC	0x0	Forwarding synchronization failed for CSI-2 output port 1 During Synchronized forwarding, this flag indicates a failure of synchronized video has been detected. For this bit to be set, the forwarding process must have previously been successful at sending at least one synchronized video frame. 0: No failure 1: Synchronization failure This bit is cleared on read.
2	FWD_SYNC_FAIL0	RC	0x0	Forwarding synchronization failed for CSI-2 output port 0 During Synchronized forwarding, this flag indicates a failure of synchronized video has been detected. For this bit to be set, the forwarding process must have previously been successful at sending at least one synchronized video frame. 0: No failure 1: Synchronization failure This bit is cleared on read.
1	FWD_SYNC1	R	0x0	Forwarding synchronized for CSI-2 output port 1 During Synchronized forwarding, this bit indicates that the forwarding engine is currently able to provide synchronized video from enabled Receive ports. This bit will always be 0 if Synchronized forwarding is disabled. 0: Video is not synchronized 1: Video is synchronized
0	FWD_SYNC0	R	0x0	Forwarding synchronized for CSI-2 output port 0 During Synchronized forwarding, this bit indicates that the forwarding engine is currently able to provide synchronized video from enabled Receive ports. This bit will always be 0 if Synchronized forwarding is disabled. 0: Video is not synchronized 1: Video is synchronized

7.6.1.36 INTERRUPT_CTL Register (Address = 0x23) [Reset = 0x00]

INTERRUPT_CTL is shown in Table 7-57.

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Table 7-57 INTERRUPT_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_EN	R/W	0x0	Global Interrupt Enable: Enables interrupt on the interrupt signal to the controller.
6	RESERVED	R	0x0	Reserved
5	IE_CSI_TX1	R/W	0x0	CSI-2 Transmit Port 1 Interrupt: Enable interrupt from CSI-2 Transmitter Port 1.
4	IE_CSI_TX0	R/W	0x0	CSI-2 Transmit Port 0 Interrupt: Enable interrupt from CSI-2 Transmitter Port 0.
3	IE_RX3	R/W	0x0	RX Port 3 Interrupt: Enable interrupt from Receiver Port 3.
2	IE_RX2	R/W	0x0	RX Port 2 Interrupt: Enable interrupt from Receiver Port 2.
1	IE_RX1	R/W	0x0	RX Port 1 Interrupt: Enable interrupt from Receiver Port 1.
0	IE_RX0	R/W	0x0	RX Port 0 Interrupt: Enable interrupt from Receiver Port 0.

7.6.1.37 INTERRUPT_STS Register (Address = 0x24) [Reset = 0x00]

INTERRUPT_STS is shown in Table 7-58.

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Table 7-58 INTERRUPT_STS Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT	R	0x0	Global Interrupt: Set if any enabled interrupt is indicated in the individual status bits in this register. The setting of this bit is not dependent on the INT_EN bit in the INTERRUPT_CTL register but does depend on the IE_xxx bits. For example, if IE_RX0 and IS_RX0 are both asserted, the INT bit is set to 1.
6	RESERVED	R	0x0	Reserved
5	IS_CSI_TX1	R	0x0	CSI-2 Transmit Port 1 Interrupt: An interrupt has occurred for CSI-2 Transmitter Port 1. This interrupt is cleared upon reading the CSI_TX_ISR register for CSI-2 Transmit Port 1.
4	IS_CSI_TX0	R	0x0	CSI-2 Transmit Port 0 Interrupt: An interrupt has occurred for CSI-2 Transmitter Port 0. This interrupt is cleared upon reading the CSI_TX_ISR register for CSI-2 Transmit Port 0.
3	IS_RX3	R	0x0	RX Port 3 Interrupt: This interrupt is cleared by reading the associated status register(s) for the event(s) that caused the interrupt. The status registers are RX_PORT_STS1, RX_PORT_STS2, and CSI_RX_STS.
2	IS_RX2	R	0x0	RX Port 2 Interrupt: An interrupt has occurred for Receive Port 2. This interrupt is cleared by reading the associated status register(s) for the event(s) that caused the interrupt. The status registers are RX_PORT_STS1, RX_PORT_STS2, and CSI_RX_STS.
1	IS_RX1	R	0x0	RX Port 1 Interrupt: An interrupt has occurred for Receive Port 1. This interrupt is cleared by reading the associated status register(s) for the event(s) that caused the interrupt. The status registers are RX_PORT_STS1, RX_PORT_STS2, and CSI_RX_STS.
0	IS_RX0	R	0x0	RX Port 0 Interrupt: An interrupt has occurred for Receive Port 0. This interrupt is cleared by reading the associated status register(s) for the event(s) that caused the interrupt. The status registers are RX_PORT_STS1, RX_PORT_STS2, and CSI_RX_STS.

7.6.1.38 TS_CONFIG Register (Address = 0x25) [Reset = 0x00]

TS_CONFIG is shown in Table 7-59.

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Table 7-59 TS_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved
6	FS_POLARITY	R/W	0x0	Framesync Polarity Indicates active edge of FrameSync signal 0: Rising edge 1: Falling edge
5:4	TS_RES_CTL	R/W	0x0	Timestamp Resolution Control 00: 40 ns 01: 80 ns 10: 160 ns 11: 1.0 us
3	TS_AS_AVAIL	R/W	0x0	Timestamp Ready Control 0: Normal operation 1: Indicate timestamps ready as soon as all port timestamps are available
2	RESERVED	R	0x0	Reserved
1	TS_FREERUN	R/W	0x0	FreeRun Mode 0: FrameSync mode 1: FreeRun mode
0	TS_MODE	R/W	0x0	Timestamp Mode 0: Line start 1: Frame start

7.6.1.39 TS_CONTROL Register (Address = 0x26) [Reset = 0x00]

TS_CONTROL is shown in Table 7-60.

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Table 7-60 TS_CONTROL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0x0	Reserved
4	TS_FREEZE	R/W	0x0	Freeze Timestamps 0: Normal operation 1: Freeze timestamps Setting this bit will freeze timestamps and clear the TS_READY flag. The TS_FREEZE bit should be cleared after reading timestamps to resume operation.
3	TS_ENABLE3	R/W	0x0	Timestamp Enable RX Port 3 0: Disabled 1: Enabled
2	TS_ENABLE2	R/W	0x0	Timestamp Enable RX Port 2 0: Disabled 1: Enabled
1	TS_ENABLE1	R/W	0x0	Timestamp Enable RX Port 1 0: Disabled 1: Enabled
0	TS_ENABLE0	R/W	0x0	Timestamp Enable RX Port 0 0: Disabled 1: Enabled

7.6.1.40 TS_LINE_HI Register (Address = 0x27) [Reset = 0x00]

TS_LINE_HI is shown in Table 7-61.

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Table 7-61 TS_LINE_HI Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	TS_LINE_HI	R/W	0x0	Timestamp Line, upper 8 bits This field is the line number at which to capture the timestamp when Line Start mode is enabled. For proper operation, the line number should be set to a value greater than 1. During Frame Start mode, if TS_FREERUN is set, the TS_LINE value is used to determine when to begin checking for Frame Start

7.6.1.41 TS_LINE_LO Register (Address = 0x28) [Reset = 0x00]

TS_LINE_LO is shown in Table 7-62.

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Table 7-62 TS_LINE_LO Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	TS_LINE_LO	R/W	0x0	Timestamp Line, lower 8 bits This field is the line number at which to capture the timestamp when Line Start mode is enabled. For proper operation, the line number should be set to a value greater than 1. During Frame Start mode, if TS_FREERUN is set, the TS_LINE value is used to determine when to begin checking for Frame Start

7.6.1.42 TS_STATUS Register (Address = 0x29) [Reset = 0x00]

TS_STATUS is shown in Table 7-63.

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Table 7-63 TS_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0x0	Reserved
4	TS_READY	R	0x0	Timestamp Ready This flag indicates when timestamps are ready to be read. This flag is cleared when the TS_FREEZE bit is set.
3	TS_VALID3	R	0x0	Timestamp Valid, RX Port 3
2	TS_VALID2	R	0x0	Timestamp Valid, RX Port 2
1	TS_VALID1	R	0x0	Timestamp Valid, RX Port 1
0	TS_VALID0	R	0x0	Timestamp Valid, RX Port 0

7.6.1.43 TIMESTAMP_P0_HI Register (Address = 0x2A) [Reset = 0x00]

TIMESTAMP_P0_HI is shown in Table 7-64.

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Table 7-64 TIMESTAMP_P0_HI Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	TIMESTAMP_P0_HI	R	0x0	Timestamp, upper 8 bits, RX Port 0

7.6.1.44 TIMESTAMP_P0_LO Register (Address = 0x2B) [Reset = 0x00]

TIMESTAMP_P0_LO is shown in Table 7-65.

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Table 7-65 TIMESTAMP_P0_LO Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	TIMESTAMP_P0_LO	R	0x0	Timestamp, lower 8 bits, RX Port 0

7.6.1.45 TIMESTAMP_P1_HI Register (Address = 0x2C) [Reset = 0x00]

TIMESTAMP_P1_HI is shown in Table 7-66.

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Table 7-66 TIMESTAMP_P1_HI Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	TIMESTAMP_P1_HI	R	0x0	Timestamp, upper 8 bits, RX Port 1

7.6.1.46 TIMESTAMP_P1_LO Register (Address = 0x2D) [Reset = 0x00]

TIMESTAMP_P1_LO is shown in Table 7-67.

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Table 7-67 TIMESTAMP_P1_LO Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	TIMESTAMP_P1_LO	R	0x0	Timestamp, lower 8 bits, RX Port 1

7.6.1.47 TIMESTAMP_P2_HI Register (Address = 0x2E) [Reset = 0x00]

TIMESTAMP_P2_HI is shown in Table 7-68.

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Table 7-68 TIMESTAMP_P2_HI Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	TIMESTAMP_P2_HI	R	0x0	Timestamp, upper 8 bits, RX Port 2

7.6.1.48 TIMESTAMP_P2_LO Register (Address = 0x2F) [Reset = 0x00]

TIMESTAMP_P2_LO is shown in Table 7-69.

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Table 7-69 TIMESTAMP_P2_LO Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	TIMESTAMP_P2_LO	R	0x0	Timestamp, lower 8 bits, RX Port 2

7.6.1.49 TIMESTAMP_P3_HI Register (Address = 0x30) [Reset = 0x00]

TIMESTAMP_P3_HI is shown in Table 7-70.

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Table 7-70 TIMESTAMP_P3_HI Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	TIMESTAMP_P3_HI	R	0x0	Timestamp, upper 8 bits, RX Port 3

7.6.1.50 TIMESTAMP_P3_LO Register (Address = 0x31) [Reset = 0x00]

TIMESTAMP_P3_LO is shown in Table 7-71.

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Table 7-71 TIMESTAMP_P3_LO Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	TIMESTAMP_P3_LO	R	0x0	Timestamp, lower 8 bits, RX Port 3

7.6.1.51 CSI_PORT_SEL Register (Address = 0x32) [Reset = 0x00]

CSI_PORT_SEL is shown in Table 7-72.

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This register selects access to Digital CSI-2 registers.

Table 7-72 CSI_PORT_SEL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0x0	Reserved
4	TX_READ_PORT	R/W	0x0	Select TX port for register read This field selects one of the two TX port register blocks for readback. This applies to the subsequent registers prefixed CSI. 0: Port 0 registers 1: Port 1 registers
3:2	RESERVED	R	0x0	Reserved
1	TX_WRITE_PORT_1	R/W	0x0	Write Enable for TX port 1 registers This bit enables writes to TX port 1 registers. Any combination of TX port registers can be written simultaneously. This applies to the subsequent registers prefixed CSI-2. 0: Writes disabled 1: Writes enabled
0	TX_WRITE_PORT_0	R/W	0x0	Write Enable for TX port 0 registers This bit enables writes to TX port 0 registers. Any combination of TX port registers can be written simultaneously. This applies to the subsequent registers prefixed CSI-2. 0: Writes disabled 1: Writes enabled

7.6.1.52 CSI_CTL Register (Address = 0x33) [Reset = 0x00]

CSI_CTL is shown in Table 7-73.

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CSI-2 TX port-specific register. The CSI-2 Port Select register 0x32 configures which unique CSI-2 TX port registers can be accessed by I2C read and write commands.

Table 7-73 CSI_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved
6	CSI_CAL_EN	R/W	0x0	Enable initial CSI-2 Skew-Calibration sequence When the initial skew-calibration sequence is enabled, the CSI-2 Transmitter will send the sequence at initialization, prior to sending any HS data. This bit must be set when operating at 1.6 Gbps CSI-2 speed (as configured in the CSI_PLL register). 0: Disabled 1: Enabled
5:4	CSI_LANE_COUNT	R/W	0x0	CSI-2 lane count 00: 4 lanes 01: 3 lanes 10: 2 lanes 11: 1 lane
3:2	CSI_ULP	R/W	0x0	Force LP00 state on data/clock lanes 00: Normal operation 01: LP00 state forced only on data lanes 10: Reserved 11: LP00 state forced on data and clock lanes
1	CSI_CONTS_CLOCK	R/W	0x0	Enable CSI-2 continuous clock mode 0: Disabled 1: Enabled NOTE: When enabled, the CSI-2 Transmitter will enter continuous clock mode upon transmission of the first packet.
0	CSI_ENABLE	R/W	0x0	Enable CSI-2 output 0: Disabled 1: Enabled NOTE: Forwarding should be disabled (via the FWD_CTL1 register) prior to enabling or disabling the CSI-2 output.

7.6.1.53 CSI_CTL2 Register (Address = 0x34) [Reset = 0x00]

CSI_CTL2 is shown in Table 7-74.

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CSI-2 TX port-specific register. The CSI-2 Port Select register 0x32 configures which unique CSI-2 TX port registers can be accessed by I2C read and write commands.

Table 7-74 CSI_CTL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0x0	Reserved
5:4	CSI_CAL_LEN	R/W	0x0	These bits control the length of the periodic calibration sequence 00: 2¹⁰ bits 01: 2¹² bits 10: 2¹⁴ bits 11: 2¹⁵ bits
3	CSI_PASS_MODE	R/W	0x0	CSI-2 PASS indication mode Determines whether the CSI-2 Pass indication is for a single port or all enabled ports. 0: Assert PASS if at least one enabled Receive port is providing valid video data 1: Assert PASS only if ALL enabled Receive ports are providing valid video data
2	CSI_CAL_INV	R/W	0x0	CSI-2 Calibration Inverted Data pattern During the CSI-2 skew-calibration pattern, the CSI-2 Transmitter will send a sequence of 01010101 data (first bit 0). Setting this bit to a 1 will invert the sequence to 10101010 data.
1	CSI_CAL_SINGLE	R/W	0x0	Enable single periodic CSI-2 Skew-Calibration sequence Setting this bit will send a single skew-calibration sequence from the CSI-2 Transmitter. The skew-calibration sequence length matches the length set for periodic calibration in CSI_CAL_LEN. The calibration sequence is sent at the next idle period on the CSI-2 interface. This bit is self-clearing and will reset to 0 after the calibration sequence is sent.
0	CSI_CAL_PERIODIC	R/W	0x0	Enable periodic CSI-2 Skew-Calibration sequence When the periodic skew-calibration sequence is enabled, the CSI-2 Transmitter will send the periodic skew-calibration sequence following the sending of Frame End packets. 0: Disabled 1: Enabled

7.6.1.54 CSI_STS Register (Address = 0x35) [Reset = 0x00]

CSI_STS is shown in Table 7-75.

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CSI-2 TX port-specific register. The CSI-2 Port Select register 0x32 configures which unique CSI-2 TX port registers can be accessed by I2C read and write commands.

Table 7-75 CSI_STS Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0x0	Reserved
4	TX_PORT_NUM	R	0x0	TX Port Number This read-only field indicates the number of the currently selected TX read port.
3:2	RESERVED	R	0x0	Reserved
1	TX_PORT_SYNC	R	0x0	TX Port Synchronized This bit indicates the CSI-2 Transmit Port is able to properly synchronize input data streams from multiple sources. This bit is 0 if synchronization is disabled via the FWD_CTL2 register. 0: Input streams are not synchronized 1: Input streams are synchronized
0	TX_PORT_PASS	R	0x0	TX Port Pass Indicates valid data is available on at least one port, or on all ports if configured for all port status via the CSI_PASS_MODE bit in the CSI_CTL2 register. The function differs based on mode of operation. In asynchronous operation, the TX_PORT_PASS indicates the CSI port is actively delivering valid video data. The status is cleared based on detection of an error condition that interrupts transmission. During Synchronized forwarding, the TX_PORT_PASS indicates valid data is available for delivery on the CSI-2 TX output. Data may not be delivered if ports are not synchronized. The TX_PORT_SYNC status is a better indicator that valid data is being delivered to the CSI-2 transmit port.

7.6.1.55 CSI_TX_ICR Register (Address = 0x36) [Reset = 0x00]

CSI_TX_ICR is shown in Table 7-76.

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CSI-2 TX port-specific register. The CSI-2 Port Select register 0x32 configures which unique CSI-2 TX port registers can be accessed by I2C read and write commands.

Table 7-76 CSI_TX_ICR Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0x0	Reserved
4	IE_RX_PORT_INT	R/W	0x0	RX Port Interrupt Enable Enable interrupt based on receiver port interrupt for the RX Ports being forwarded to the CSI-2 Transmit Port.
3	IE_CSI_SYNC_ERROR	R/W	0x0	CSI-2 Sync Error interrupt Enable Enable interrupt on CSI-2 Synchronization enable.
2	IE_CSI_SYNC	R/W	0x0	CSI-2 Synchronized interrupt Enable Enable interrupts on CSI-2 Transmit Port assertion of CSI-2 Synchronized Status.
1	IE_CSI_PASS_ERROR	R/W	0x0	CSI-2 RX Pass Error interrupt Enable Enable interrupt on CSI-2 Pass Error
0	IE_CSI_PASS	R/W	0x0	CSI-2 Pass interrupt Enable Enable interrupt on CSI-2 Transmit Port assertion of CSI-2 Pass.

7.6.1.56 CSI_TX_ISR Register (Address = 0x37) [Reset = 0x00]

CSI_TX_ISR is shown in Table 7-77.

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CSI-2 TX port-specific register. The CSI-2 Port Select register 0x32 configures which unique CSI-2 TX port registers can be accessed by I2C read and write commands.

Table 7-77 CSI_TX_ISR Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0x0	Reserved
4	IS_RX_PORT_INT	R	0x0	RX Port Interrupt A Receiver port interrupt has been generated for one of the RX Ports being forwarded to the CSI-2 Transmit Port. A read of the associated port receive status registers will clear this interrupt. See the PORT_ISR_HI and PORT_ISR_LO registers for details.
3	IS_CSI_SYNC_ERROR	RC	0x0	CSI-2 Sync Error interrupt A synchronization error has been detected for multiple video stream inputs to the CSI-2 Transmitter.
2	IS_CSI_SYNC	RC	0x0	CSI-2 Synchronized interrupt CSI-2 Transmit Port assertion of CSI-2 Synchronized Status. Current status for CSI-2 Sync can be read from the TX_PORT_SYNC flag in the CSI_STS register.
1	IS_CSI_PASS_ERROR	RC	0x0	CSI-2 RX Pass Error interrupt A deassertion of CSI-2 Pass has been detected on one of the RX Ports being forwarded to the CSI-2 Transmit Port
0	IS_CSI_PASS	RC	0x0	CSI-2 Pass interrupt CSI-2 Transmit Port assertion of CSI-2 Pass detected. Current status for the CSI-2 Pass indication can be read from the TX_PORT_PASS flag in the CSI_STS register

7.6.1.57 SFILTER_CFG Register (Address = 0x41) [Reset = 0xA9]

SFILTER_CFG is shown in Table 7-78.

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Table 7-78 SFILTER_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	SFILTER_MAX	R/W	0xA	SFILTER Maximum setting This field controls the maximum SFILTER setting. Allowed values are 0-14 with 7 being the mid point. These values are used for both AEQ adaption and dynamic SFILTER control. The maximum setting must be greater than of equal to the SFILTER_MIN.
3:0	SFILTER_MIN	R/W	0x9	SFILTER Minimum setting This field controls the minimum SFILTER setting. Allowed values are 0-14, where 7 is the mid point. These values are used for both AEQ adaption and dynamic SFILTER control. The minimum setting must be less than or equal to the SFILTER_MAX.

7.6.1.58 AEQ_CTL Register (Address = 0x42) [Reset = 0x71]

AEQ_CTL is shown in Table 7-79.

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Table 7-79 AEQ_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved
6:4	AEQ_ERR_CTL	R/W	0x7	AEQ Error Control Setting any of these bits will enable V3LINK error checking during the Adaptive Equalization process. Errors are accumulated over 1/2 of the period of the timer set by the ADAPTIVE_EQ_RELOCK_TIME filed in the AEQ_TEST register. If the number of errors is greater than the programmed threshold (AEQ_ERR_THOLD), the AEQ will attempt to increase the EQ setting. The errors may also be checked as part of EQ setting validation if AEQ_2STEP_EN is set. The following errors are checked based on this three bit field: [2] V3LINK clk1/clk0 errors [1] DCA sequence errors [0] Parity errors
3	AEQ_SFIL_ORDER	R/W	0x0	AEQ SFILTER Adapt order This bit controls the order of adaption for SFILTER values during Adaptive Equalization. 0: Default order, start at largest clock delay 1: Start at midpoint, no additional clock or data delay
2	AEQ_2STEP_EN	R/W	0x0	AEQ 2-step enable This bit enables a two-step operation as part of the Adaptive EQ algorithm. If disabled, the state machine will wait for a programmed period of time, then check status to determine if setting is valid. If enabled, the state machine will wait for 1/2 the programmed period, then check for errors over an additional 1/2 the programmed period. If errors occur during the 2nd step, the state machine will immediately move to the next setting. 0: Wait for full programmed delay, then check instantaneous lock value 1: Wait for 1/2 programmed time, then check for errors over 1/2 programmed time. The programmed time is controlled by the ADAPTIVE_EQ_RELOCK_TIME field in the AEQ_TEST register
1	AEQ_OUTER_LOOP	R/W	0x0	AEQ outer loop control This bit controls whether the Equalizer or SFILTER adaption is the outer loop when the AEQ adaption includes SFILTER adaption. 0: AEQ is inner loop, SFILTER is outer loop 1: AEQ is outer loop, SFILTER is inner loop
0	AEQ_SFILTER_EN	R/W	0x1	Enable SFILTER Adaption with AEQ Setting this bit allows SFILTER adaption as part of the Adaptive Equalizer algorithm.

7.6.1.59 AEQ_ERR_THOLD Register (Address = 0x43) [Reset = 0x01]

AEQ_ERR_THOLD is shown in Table 7-80.

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Table 7-80 AEQ_ERR_THOLD Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	AEQ_ERR_THRESHOLD	R/W	0x1	AEQ Error Trheshold This register controls the error threshold to determine when to re-adapt the EQ settings. This register must not be programmed to a value of 0.

7.6.1.60 BCC_ERR_CTL Register (Address = 0x46) [Reset = 0x20]

BCC_ERR_CTL is shown in Table 7-81.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-81 BCC_ERR_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BCC_ACK_REMOTE_READ	R/W	0x0	Enable Control Channel to acknowledge start of remote read. When operating with a link partner that supports Enhanced Error Checking for the Bidirectional Control Channel, setting this bit allows the Deserializer to generate an internal acknowlege to the beginning of a remote I2C target read. This allows additional error detection at the Seserializer. This bit should not be set when operating with Serializers that do not support Enhanced Error Checking. 0: Disable 1: Enable
6	BCC_EN_DATA_CHK	R/W	0x0	Enable checking of returned data Enhanced Error checking can check for errors on returned data during an acknowledge cycle for data sent to remote devices over the Bidirectional Control Channel. In addition, If an error is detected, this register control will allow changing a remote Ack to a Nack to indicate the data error on the local I2C interface. This bit must not be set when operating with Serializers that do not support Enhanced Error checking as they will not always return the correct data during an Ack. 0: Disable returned data error detection 1: Enable returned data error detection
5	BCC_EN_ENH_ERROR	R/W	0x1	Enable Enhanced Error checking in Bidirection Control Channel The Bidirectional Control Channel can detect certain error conditions and terminate transactions if an error is detected. This capability can be disabled by setting this bit to 0. 0: Disable Enhanced Error checking 1: Enable Enhanced Error checking
4:3	FORCE_BCC_ERROR	R/W	0x0	BCC Force Error The BCC Force Error control causes an error to be forced on the BCC over the back channel. 00: No error 01: Force CRC Error on BCC frame= BCC_FRAME_SEL 10: Force CRC Error on normal frame following BCC frame= BCC_FRAME_SEL 11: FORCE Data Error on BCC frame= BCC_FRAME_SEL Setting this control generates a single error on the back channel signaling.
2:0	BCC_FRAME_SEL	R/W	0x0	BCC Frame Select The BCC Frame Select allows selection of the forward channel BCC frame which will include the error condition selected in the force control bits of this register. BCC transfers are sent in bytes for each block transferred. This value may be set in range of 0 to 7 to force an error on any of the first 8 bytes sent on the BCC forward channel.

7.6.1.61 BCC_STATUS Register (Address = 0x47) [Reset = 0x00]

BCC_STATUS is shown in Table 7-82.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-82 BCC_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0x0	Reserved
5	BCC_SEQ_ERROR	RC	0x0	Bidirectional Control Channel Sequence Error Detected This bit indicates a sequence error has been detected in the forward control channel. If this bit is set, an error may have occurred in the control channel operation. If BCC_EN_ENH_ERR is 0 (disabled), this register is read-only copy of the BCC_SEQ_ERROR bit in the RX_PORT_STS1 register. If BCC_EN_ENH_ERR is 1 (enabled), this register is cleared on read of this register.
4	BCC_CONTROLLER_ERR	RC	0x0	BCC Controller Error This flag indicates a Forward Channel BCC Sequence, BCC CRC, or Lock error occurred while waiting for a response from the Serializer while the BCC I2C Controller is active. This flag is cleared on read of this register. This indication is available only if BCC_EN_ENH_ERR is set to 1.
3	BCC_CONTROLLER_TO	RC	0x0	BCC Controller Timeout Error This bit will be set if the BCC Watchdog Timer expires will waiting for a response from the Serializer while the BCC I2C Controller is active. This flag is cleared on read of this register. This indication is available only if BCC_EN_ENH_ERR is set to 1.
2	BCC_TARGET_ERR	RC	0x0	BCC Target Error This flag indicates a Forward Channel BCC Sequence, BCC CRC, or Lock error occurred while waiting for a response from the Serializer while the BCC I2C Target is active. This flag is cleared on read of this register. This indication is available only if BCC_EN_ENH_ERR is set to 1.
1	BCC_TARGET_TO	RC	0x0	BCC Target Timeout Error This bit will be set if the BCC Watchdog Timer expires will waiting for a response from the Serializer while the BCC I2C Target is active. This flag is cleared on read of this register.
0	BCC_RESP_ERR	RC	0x0	BCC Response Error This flag indicates an error has been detected in response to a command on the Bidirectional Control Channel. When the I2C Target is active, the Serializer should return data written (I2C address, offset, or data). When the I2C Target is active, the Serializer will return data read. The BCC function checks the returned data for errors, and will set this flag if an error is detected. This flag is cleared on read of this register. This indication is available only if BCC_EN_ENH_ERR is set to 1.

7.6.1.62 V3LINK_CAP Register (Address = 0x4A) [Reset = 0x00]

V3LINK_CAP is shown in Table 7-83.

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Table 7-83 V3LINK_CAP Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0x0	Reserved
4	V3LINK_ENC_CRC_CAP	R/W	0x0	0: Disable CRC error flag from V3LINK encoder 1: Enable CRC error flag from V3LINK encoder (recommended)
3	RESERVED	R	0x0	Reserved
2	RESERVED	R	0x0	Reserved
1:0	RESERVED	R	0x0	Reserved

7.6.1.63 RAW_EMBED_DTYPE Register (Address = 0x4B) [Reset = 0x12]

RAW_EMBED_DTYPE is shown in Table 7-84.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands. When the receiver is programmed for Raw mode data, this register field allows setting the Data Type field for the first N lines to indicated embedded non-image data. RAW_EMBED_DTYPE has no effect on CSI-2 receiver modes.

Table 7-84 RAW_EMBED_DTYPE Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	EMBED_DTYPE_EN	R/W	0x0	Embeded Data Type Enable 0: All long packets will be forwarded as RAW10 or RAW12 video data 01, 10, or 11: Send first N long packets (1, 2, or 3) as Embedded data using the data type in the EMBED_DTYPE_ID field of this register. This control has no effect if the Receiver is programmed to receive CSI-2 formatted data.
5:0	EMBED_DTYPE_ID	R/W	0x12	Embedded Data Type If sending embedded data is enabled via the EMBED_DTYPE_EN control in this register, the Data Type field for the first N lines of each frame will use this value rather than the value programmed in the RAW12_ID or RAW10_ID registers. The default setting matches the CSI-2 specification for Embedded 8-bit non Image Data.

7.6.1.64 V3LINK_PORT_SEL Register (Address = 0x4C) [Reset = 0x00]

V3LINK_PORT_SEL is shown in Table 7-85.

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The V3Link Port Select register configures which port is accessed in I2C commands to unique Rx Port registers 0x4D - 0x7F and 0xD0 - 0xDF. A 2-bit RX_READ_PORT field provides for reading values from a single port. The RX_WRITE_PORT fields provide individual enables for each port, allowing simultaneous writes broadcast to all of the V3Link Receive port register blocks in unison. The TDES960 maintains separate page control, preventing conflict between sources.

Table 7-85 V3LINK_PORT_SEL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	PHYS_PORT_NUM	R	0x0	Physical port number This field porvides the physical port connection when reading from a remote device via the Bi-directional Control Channel. When accessed via local I2C interfaces, the value returned is always 0. When accessed via Bi-directional Control Channel, the value returned is the port number of the Receive port connection.
5:4	RX_READ_PORT	R/W	0x0	Select RX port for register read This field selects one of the four RX port register blocks for readback. This applies to all paged V3LINK Receiver port registers. 00: Port 0 registers 01: Port 1 registers 10: Port 2 registers 11: Port 3 registers When accessed via local I2C interfaces, the default setting is 0. When accessed via Bi-directional Control Channel, the default value is the port number of the Receive port connection.
3	RX_WRITE_PORT_3	R/W	0x0	Write Enable for RX port 3 registers This bit enables writes to RX port 3 registers. Any combination of RX port registers can be written simultaneously. This applies to all paged V3LINK Receiver port registers. 0: Writes disabled 1: Writes enabled When accessed via Bi-directional Control Channel, the default value is 1 if accessed over RX port 3.
2	RX_WRITE_PORT_2	R/W	0x0	Write Enable for RX port 2 registers This bit enables writes to RX port 2 registers. Any combination of RX port registers can be written simultaneously. This applies to all paged V3LINK Receiver port registers. 0: Writes disabled 1: Writes enabled When accessed via Bi-directional Control Channel, the default value is 1 if accessed over RX port 2.
1	RX_WRITE_PORT_1	R/W	0x0	Write Enable for RX port 1 registers This bit enables writes to RX port 1 registers. Any combination of RX port registers can be written simultaneously. This applies to all paged V3LINK Receiver port registers. 0: Writes disabled 1: Writes enabled When accessed via Bi-directional Control Channel, the default value is 1 if accessed over RX port 1.
0	RX_WRITE_PORT_0	R/W	0x0	Write Enable for RX port 0 registers This bit enables writes to RX port 0 registers. Any combination of RX port registers can be written simultaneously. This applies to all paged V3LINK Receiver port registers. 0: Writes disabled 1: Writes enabled When accessed via Bi-directional Control Channel, the default value is 1 if accessed over RX port 0.

7.6.1.65 RX_PORT_STS1 Register (Address = 0x4D) [Reset = 0x00]

RX_PORT_STS1 is shown in Table 7-86.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-86 RX_PORT_STS1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RX_PORT_NUM	R	0x0	RX Port Number This read-only field indicates the number of the currently selected RX read port.
5	BCC_CRC_ERROR	RC	0x0	Bi-directional Control Channel CRC Error Detected This bit indicates a CRC error has been detected in the forward control channel. If this bit is set, an error may have occurred in the control channel operation. This bit is cleared on read.
4	LOCK_STS_CHG	RC	0x0	Lock Status Changed This bit is set if a change in receiver lock status has been detected since the last read of this register. Current lock status is available in the LOCK_STS bit of this register This bit is cleared on read.
3	BCC_SEQ_ERROR/BCC_ERROR	RC	0x0	The function of this bit depends on the setting of the BCC_EN_ENH_ERR control in the BCC_ERR_CTL register. If BCC_EN_ENH_ERR is 0 (disabled), this register is defined as follows: Bidirectional Control Channel Sequence Error Detected This bit indicates a sequence error has been detected in the forward control channel. If this bit is set, an error may have occurred in the control channel operation. This bit is cleared on read. If BCC_EN_ENH_ERR is 1 (enabled), this register is defined as follows: Bidirectional Control Channel Error Flag This flag indicates one or more errors have been detected during Bidirectional Control Channel communication with the Deserializer. The BCC_STATUS register contains further information on the type of error detected. This bit will be cleared upon read of the BCC_STATUS register.
2	PARITY_ERROR	R	0x0	V3LINK parity errors detected This flag is set when the number of parity errors detected is greater than the threshold programmed in the PAR_ERR_THOLD registers. 1: Number of V3LINK parity errors detected is greater than the threshold 0: Number of V3LINK parity errors is below the threshold This bit is cleared when the RX_PAR_ERR_HI/LO registers are cleared.
1	PORT_PASS	R	0x0	Receiver PASS indication This bit indicates the current status of the Receiver PASS indication. The requirements for setting the Receiver PASS indication are controlled by the PORT_PASS_CTL register. 1: Receive input has met PASS criteria 0: Receive input does not meet PASS criteria
0	LOCK_STS	R	0x0	V3LINK receiver is locked to incoming data 1: Receiver is locked to incoming data 0: Receiver is not locked

7.6.1.66 RX_PORT_STS2 Register (Address = 0x4E) [Reset = 0x00]

RX_PORT_STS2 is shown in Table 7-87.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-87 RX_PORT_STS2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	LINE_LEN_UNSTABLE	RC	0x0	Line Length Unstable If set, this bit indicates the line length was detected as unstable during a previous video frame. The line length is considered to be stable if all the lines in the video frame have the same length. This flag will remain set until read.
6	LINE_LEN_CHG	RC	0x0	Line Length Changed 1: Change of line length detected 0: Change of line length not detected This bit is cleared on read.
5	V3LINK_ENCODE_ERROR	RC	0x0	V3LINK Encoder error detected If set, this flag indicates an error in the V3Link encoding has been detected by the V3Link receiver. Tihs bit is cleared on read. Note, to detect V3Link Encoder errors, the LINK_ERROR_COUNT must be enabled with a LINK_ERR_THRESH value greater than 1. Otherwise, the loss of Receiver Lock will prevent detection of the Encoder error.
4	BUFFER_ERROR	RC	0x0	Packet buffer error detected. If this bit is set, an overflow condition has occurred on the packet buffer FIFO. 1: Packet Buffer error detected 0: No Packet Buffer errors detected This bit is cleared on read.
3	CSI_ERROR	R	0x0	CSI-2 Receive error detected See the CSI_RX_STS register for details.
2	FREQ_STABLE	R	0x0	Frequency measurement stable
1	NO_V3LINK_CLK	R	0x0	No V3Link input clock detected When set, this bit indicates that no V3Link Clock has been detected. This bit will be set if the input frequency is below the setting programmed in the FREQ_LO_THR setting in the FREQ_DET_CTL register.
0	LINE_CNT_CHG	RC	0x0	Line Count Changed 1: Change of line count detected 0: Change of line count not detected This bit is cleared on read.

7.6.1.67 RX_FREQ_HIGH Register (Address = 0x4F) [Reset = 0x00]

RX_FREQ_HIGH is shown in Table 7-88.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-88 RX_FREQ_HIGH Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	FREQ_CNT_HIGH	R	0x0	Frequency Counter High Byte (MHz) The Frequency counter reports the measured frequency for the V3LINK Receiver. This portion of the field is the integer value in MHz.

7.6.1.68 RX_FREQ_LOW Register (Address = 0x50) [Reset = 0x00]

RX_FREQ_LOW is shown in Table 7-89.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-89 RX_FREQ_LOW Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	FREQ_CNT_LOW	R	0x0	Frequency Counter Low Byte (1/256 MHz) The Frequency counter reports the measured frequency for the V3LINK Receiver. This portion of the field is the fractional value in 1/256 MHz.

7.6.1.69 SENSOR_STS_0 Register (Address = 0x51) [Reset = 0x00]

SENSOR_STS_0 is shown in Table 7-90.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands. Sensor Status Register 0 field provides additional status information when paired with a TSER953 Serializer. This field is automatically loaded from the forward channel.

Table 7-90 SENSOR_STS_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	SENSOR_STS_0	R	0x0	Sensor Status Register 0 This field provides status from the Serializer. It is automatically loaded from the forward channel. Refer to the Serializer Datasheet

7.6.1.70 SENSOR_STS_1 Register (Address = 0x52) [Reset = 0x00]

SENSOR_STS_1 is shown in Table 7-91.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands. Sensor Status Register 1 field provides additional status information when paired with a TSER953 Serializer. This field is automatically loaded from the forward channel.

Table 7-91 SENSOR_STS_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	SENSOR_STS_1	R	0x0	Sensor Status Register 1 This field provides status from the Serializer. It is automatically loaded from the forward channel. Refer to the Serializer Datasheet

7.6.1.71 SENSOR_STS_2 Register (Address = 0x53) [Reset = 0x00]

SENSOR_STS_2 is shown in Table 7-92.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands. Sensor Status Register 2 field provides additional status information when paired with a TSER953 Serializer. This field is automatically loaded from the forward channel.

Table 7-92 SENSOR_STS_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	SENSOR_STS_2	R	0x0	Sensor Status Register 2 This field provides status from the Serializer. It is automatically loaded from the forward channel. Refer to the Serializer Datasheet

7.6.1.72 SENSOR_STS_3 Register (Address = 0x54) [Reset = 0x00]

SENSOR_STS_3 is shown in Table 7-93.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands. Sensor Status Register 3 field provides additional status information on the CSI-2 input when paired with a TSER953 Serializer. This field is automatically loaded from the forward channel.

Table 7-93 SENSOR_STS_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	SENSOR_STS_3	R	0x0	Sensor Status Register 3 This field provides status from the Serializer. It is automatically loaded from the forward channel. Refer to the Serializer Datasheet

7.6.1.73 RX_PAR_ERR_HI Register (Address = 0x55) [Reset = 0x00]

RX_PAR_ERR_HI is shown in Table 7-94.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-94 RX_PAR_ERR_HI Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PAR_ERROR_BYTE_1	R	0x0	Number of V3LINK parity errors – 8 most significant bits The parity error counter registers return the number of data parity errors that have been detected on the V3LINK Receiver data since the last detection of valid lock or last read of the RX_PAR_ERR_LO register. For accurate reading of the parity error count, disable the RX PARITY CHECKER ENABLE bit in register 0x2 prior to reading the parity error count registers. This register is cleared upon reading the RX_PAR_ERR_LO register.

7.6.1.74 RX_PAR_ERR_LO Register (Address = 0x56) [Reset = 0x00]

RX_PAR_ERR_LO is shown in Table 7-95.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-95 RX_PAR_ERR_LO Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PAR_ERROR_BYTE_0	RC	0x0	Number of V3LINK parity errors – 8 least significant bits The parity error counter registers return the number of data parity errors that have been detected on the V3LINK Receiver data since the last detection of valid lock or last read of the RX_PAR_ERR_LO register. For accurate reading of the parity error count, disable the RX PARITY CHECKER ENABLE bit in register 0x2 prior to reading the parity error count registers. This register is cleared on read.

7.6.1.75 BIST_ERR_COUNT Register (Address = 0x57) [Reset = 0x00]

BIST_ERR_COUNT is shown in Table 7-96.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-96 BIST_ERR_COUNT Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	BIST_ERROR_COUNT	R	0x0	Bist Error Count Returns BIST error count

7.6.1.76 BCC_CONFIG Register (Address = 0x58) [Reset = 0x1X]

BCC_CONFIG is shown in Table 7-97.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-97 BCC_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	I2C_PASS_THROUGH_ALL	R/W	0x0	I2C Pass-Through All Transactions 0: Disabled 1: Enabled
6	I2C_PASS_THROUGH	R/W	0x0	I2C Pass-Through to Serializer if decode matches 0: Pass-Through Disabled 1: Pass-Through Enabled
5	AUTO_ACK_ALL	R/W	0x0	Automatically Acknowledge all I2C writes independent of the forward channel lock state or status of the remote Acknowledge 1: Enable 0: Disable
4	BC_ALWAYS_ON	R/W	0x1	Back channel enable 1: Back channel is always enabled independent of I2C_PASS_THROUGH and I2C_PASS_THROUGH_ALL 0: Back channel enable requires setting of either I2C_PASS_THROUGH and I2C_PASS_THROUGH_ALL This bit may only be written via a local I2C controller.
3	BC_CRC_GEN_ENABLE	R/W	0x1	Back Channel CRC Generator Enable 0: Disable 1: Enable
2:0	BC_FREQ_SELECT	R/WStrap	X	Back Channel Frequency Select (Strap) 000: 2.5 Mbps (default for TSER953 compatibility) 001: Reserved 010: 10 Mbps 011: Reserved 100: Reserved 101: Reserved 110: 50 Mbps (default for TSER953 compatibility) 111: Reserved Note that changing this setting will result in some errors on the back channel for a short period of time. If set over the control channel, the Deserializer will first be programmed to Auto-Ack operation to avoid a control channel timeout due to lack of response from the Serializer. invalid

7.6.1.77 DATAPATH_CTL1 Register (Address = 0x59) [Reset = 0x00]

DATAPATH_CTL1 is shown in Table 7-98.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-98 DATAPATH_CTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OVERRIDE_FC_CONFIG	R/W	0x0	1: Disable loading of the DATAPATH_CTL registers from the forward channel, keeping locally written values intact 0: Allow forward channel loading of DATAPATH_CTL registers
6:2	RESERVED	R	0x0	Reserved
1:0	FC_GPIO_EN	R/W	0x0	Forward Channel GPIO Enable Configures the number of enabled forward channel GPIOs 00: GPIOs disabled 01: One GPIO 10: Two GPIOs 11: Four GPIOs This field is normally loaded from the remote serializer. It can be overwritten if the OVERRIDE_FC_CONFIG bit in this register is 1.

7.6.1.78 SER_ID Register (Address = 0x5B) [Reset = 0x00]

SER_ID is shown in Table 7-99.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-99 SER_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	SER_ID	R/W	0x0	Remote Serializer ID This field is normally loaded automatically from the remote Serializer.
0	FREEZE_DEVICE_ID	R/W	0x0	Freeze Serializer Device ID Prevent auto-loading of the Serializer Device ID from the Forward Channel. The ID is frozen at the value written.

7.6.1.79 SER_ALIAS_ID Register (Address = 0x5C) [Reset = 0x00]

SER_ALIAS_ID is shown in Table 7-100.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-100 SER_ALIAS_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	SER_ALIAS_ID	R/W	0x0	7-bit Remote Serializer Alias ID Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Deserializer. The transaction is remapped to the address specified in the Target ID register. A value of 0 in this field disables access to the remote I2C Target.
0	SER_AUTO_ACK	R/W	0x0	Automatically Acknowledge all I2C writes to the remote Serializer independent of the forward channel lock state or status of the remote Serializer Acknowledge 1: Enable 0: Disable

7.6.1.80 TARGET_ID_0 Register (Address = 0x5D) [Reset = 0x00]

TARGET_ID_0 is shown in Table 7-101.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-101 TARGET_ID_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	TARGET_ID0	R/W	0x0	7-bit Remote Target Device ID 0 Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID0, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0	RESERVED	R	0x0	Reserved

7.6.1.81 TARGET_ID_1 Register (Address = 0x5E) [Reset = 0x00]

TARGET_ID_1 is shown in Table 7-102.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-102 TARGET_ID_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	TARGET_ID1	R/W	0x0	7-bit Remote Target Device ID 1 Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID1, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0	RESERVED	R	0x0	Reserved

7.6.1.82 TARGET_ID_2 Register (Address = 0x5F) [Reset = 0x00]

TARGET_ID_2 is shown in Table 7-103.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-103 TARGET_ID_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	TARGET_ID2	R/W	0x0	7-bit Remote Target Device ID 2 Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID2, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0	RESERVED	R	0x0	Reserved

7.6.1.83 TARGET_ID_3 Register (Address = 0x60) [Reset = 0x00]

TARGET_ID_3 is shown in Table 7-104.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-104 TARGET_ID_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	TARGET_ID3	R/W	0x0	7-bit Remote Target Device ID 3 Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID3, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0	RESERVED	R	0x0	Reserved

7.6.1.84 TARGET_ID_4 Register (Address = 0x61) [Reset = 0x00]

TARGET_ID_4 is shown in Table 7-105.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-105 TARGET_ID_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	TARGET_ID4	R/W	0x0	7-bit Remote Target Device ID 4 Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID4, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0	RESERVED	R	0x0	Reserved

7.6.1.85 TARGET_ID_5 Register (Address = 0x62) [Reset = 0x00]

TARGET_ID_5 is shown in Table 7-106.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-106 TARGET_ID_5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	TARGET_ID5	R/W	0x0	7-bit Remote Target Device ID 5 Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID5, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0	RESERVED	R	0x0	Reserved

7.6.1.86 TARGET_ID_6 Register (Address = 0x63) [Reset = 0x00]

TARGET_ID_6 is shown in Table 7-107.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-107 TARGET_ID_6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	TARGET_ID6	R/W	0x0	7-bit Remote Target Device ID 6 Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID6, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0	RESERVED	R	0x0	Reserved

7.6.1.87 TARGET_ID_7 Register (Address = 0x64) [Reset = 0x00]

TARGET_ID_7 is shown in Table 7-108.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-108 TARGET_ID_7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	TARGET_ID7	R/W	0x0	7-bit Remote Target Device ID 7 Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID7, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer.
0	RESERVED	R	0x0	Reserved

7.6.1.88 TARGET_ALIAS_0 Register (Address = 0x65) [Reset = 0x00]

TARGET_ALIAS_0 is shown in Table 7-109.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-109 TARGET_ALIAS_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	TARGET_ALIAS_ID0	R/W	0x0	7-bit Remote Target Device Alias ID 0 Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction is remapped to the address specified in the Target ID0 register. A value of 0 in this field disables access to the remote I2C Target.
0	TARGET_AUTO_ACK_0	R/W	0x0	Automatically Acknowledge all I2C writes to the remote Target 0 independent of the forward channel lock state or status of the remote Serializer Acknowledge 1: Enable 0: Disable

7.6.1.89 TARGET_ALIAS_1 Register (Address = 0x66) [Reset = 0x00]

TARGET_ALIAS_1 is shown in Table 7-110.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-110 TARGET_ALIAS_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	TARGET_ALIAS_ID1	R/W	0x0	7-bit Remote Target Device Alias ID 1 Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction is remapped to the address specified in the Target ID1 register. A value of 0 in this field disables access to the remote I2C Target.
0	TARGET_AUTO_ACK_1	R/W	0x0	Automatically Acknowledge all I2C writes to the remote Target 1 independent of the forward channel lock state or status of the remote Serializer Acknowledge 1: Enable 0: Disable

7.6.1.90 TARGET_ALIAS_2 Register (Address = 0x67) [Reset = 0x00]

TARGET_ALIAS_2 is shown in Table 7-111.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-111 TARGET_ALIAS_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	TARGET_ALIAS_ID2	R/W	0x0	7-bit Remote Target Device Alias ID 2 Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction is remapped to the address specified in the Target ID2 register. A value of 0 in this field disables access to the remote I2C Target.
0	TARGET_AUTO_ACK_2	R/W	0x0	Automatically Acknowledge all I2C writes to the remote Target 2 independent of the forward channel lock state or status of the remote Serializer Acknowledge 1: Enable 0: Disable

7.6.1.91 TARGET_ALIAS_3 Register (Address = 0x68) [Reset = 0x00]

TARGET_ALIAS_3 is shown in Table 7-112.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-112 TARGET_ALIAS_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	TARGET_ALIAS_ID3	R/W	0x0	7-bit Remote Target Device Alias ID 3 Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction is remapped to the address specified in the Target ID3 register. A value of 0 in this field disables access to the remote I2C Target.
0	TARGET_AUTO_ACK_3	R/W	0x0	Automatically Acknowledge all I2C writes to the remote Target 3 independent of the forward channel lock state or status of the remote Serializer Acknowledge 1: Enable 0: Disable

7.6.1.92 TARGET_ALIAS_4 Register (Address = 0x69) [Reset = 0x00]

TARGET_ALIAS_4 is shown in Table 7-113.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-113 TARGET_ALIAS_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	TARGET_ALIAS_ID4	R/W	0x0	7-bit Remote Target Device Alias ID 4 Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction is remapped to the address specified in the Target ID4 register. A value of 0 in this field disables access to the remote I2C Target.
0	TARGET_AUTO_ACK_4	R/W	0x0	Automatically Acknowledge all I2C writes to the remote Target 4 independent of the forward channel lock state or status of the remote Serializer Acknowledge 1: Enable 0: Disable

7.6.1.93 TARGET_ALIAS_5 Register (Address = 0x6A) [Reset = 0x00]

TARGET_ALIAS_5 is shown in Table 7-114.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-114 TARGET_ALIAS_5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	TARGET_ALIAS_ID5	R/W	0x0	7-bit Remote Target Device Alias ID 5 Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction is remapped to the address specified in the Target ID5 register. A value of 0 in this field disables access to the remote I2C Target.
0	TARGET_AUTO_ACK_5	R/W	0x0	Automatically Acknowledge all I2C writes to the remote Target 5 independent of the forward channel lock state or status of the remote Serializer Acknowledge 1: Enable 0: Disable

7.6.1.94 TARGET_ALIAS_6 Register (Address = 0x6B) [Reset = 0x00]

TARGET_ALIAS_6 is shown in Table 7-115.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-115 TARGET_ALIAS_6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	TARGET_ALIAS_ID6	R/W	0x0	7-bit Remote Target Device Alias ID 6 Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction is remapped to the address specified in the Target ID6 register. A value of 0 in this field disables access to the remote I2C Target.
0	TARGET_AUTO_ACK_6	R/W	0x0	Automatically Acknowledge all I2C writes to the remote Target 6 independent of the forward channel lock state or status of the remote Serializer Acknowledge 1: Enable 0: Disable

7.6.1.95 TARGET_ALIAS_7 Register (Address = 0x6C) [Reset = 0x00]

TARGET_ALIAS_7 is shown in Table 7-116.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-116 TARGET_ALIAS_7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	TARGET_ALIAS_ID7	R/W	0x0	7-bit Remote Target Device Alias ID 7 Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction is remapped to the address specified in the Target ID7 register. A value of 0 in this field disables access to the remote I2C Target.
0	TARGET_AUTO_ACK_7	R/W	0x0	Automatically Acknowledge all I2C writes to the remote Target 7 independent of the forward channel lock state or status of the remote Serializer Acknowledge 1: Enable 0: Disable

7.6.1.96 PORT_CONFIG Register (Address = 0x6D) [Reset = 0x7X]

PORT_CONFIG is shown in Table 7-117.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-117 PORT_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	CSI_WAIT_FS1	R/W	0x0	CSI-2 Wait for FrameStart packet with count 1 The CSI-2 Receiver will wait for a Frame Start packet with count of 1 before accepting other packets This bit has no effect in RAW V3LINK input modes.
6	CSI_WAIT_FS	R/W	0x1	CSI-2 Wait for FrameStart packet CSI2 Receiver will wait for a Frame Start packet before accepting other packets This bit has no effect in RAW V3LINK input modes.
5	CSI_FWD_CKSUM	R/W	0x1	Forward CSI-2 packets with checksum errors 0: Do not forward errored packets 1: Forward errored packets This bit has no effect in RAW V3LINK input modes.
4	CSI_FWD_ECC	R/W	0x1	Forward CSI-2 packets with ECC errors 0: Do not forward errored packets 1: Forward errored packets
3	DISCARD_1ST_LINE_ON_ERR/CSI_FWD_LEN	R/W	0x1	In RAW Mode, Discard first video line if FV to LV setup time is not met. 0: Forward truncated 1st video line 1: Discard truncated 1st video line In V3LINK CSI-2 Mode, Forward CSI-2 packets with length errors 0: Do not forward errored packets 1: Forward errored packets
2	RESERVED	R	0x0	Reserved invalid
1:0	V3LINK_MODE	R/WStrap	X	V3LINK Input Mode (Strap) 00: CSI-2 Mode (TSER953 compatible) 01: RAW12 Low Frequency Mode (DVP Mode serializer compatible) 10: RAW12 High Frequency Mode (DVP Mode serializer compatible) 11: RAW10 Mode (DVP Mode serializer compatible) invalid

7.6.1.97 BC_GPIO_CTL0 Register (Address = 0x6E) [Reset = 0x88]

BC_GPIO_CTL0 is shown in Table 7-118.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-118 BC_GPIO_CTL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	BC_GPIO1_SEL	R/W	0x8	Back channel GPIO1 Select: Determines the data sent on GPIO1 for the port back channel. 0xxx: Pin GPIOx where x is BC_GPIO1_SEL[2:0] 1000: Constant value of 0 1001: Constant value of 1 1010: FrameSync signal 1011 - 1111: Reserved
3:0	BC_GPIO0_SEL	R/W	0x8	Back channel GPIO0 Select: Determines the data sent on GPIO0 for the port back channel. 0xxx: Pin GPIOx where x is BC_GPIO0_SEL[2:0] 1000: Constant value of 0 1001: Constant value of 1 1010: FrameSync signal 1011 - 1111: Reserved

7.6.1.98 BC_GPIO_CTL1 Register (Address = 0x6F) [Reset = 0x88]

BC_GPIO_CTL1 is shown in Table 7-119.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-119 BC_GPIO_CTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	BC_GPIO3_SEL	R/W	0x8	Back channel GPIO3 Select: Determines the data sent on GPIO3 for the port back channel. 0xxx: Pin GPIOx where x is BC_GPIO3_SEL[2:0] 1000: Constant value of 0 1001: Constant value of 1 1010: FrameSync signal 1011 - 1111: Reserved
3:0	BC_GPIO2_SEL	R/W	0x8	Back channel GPIO2 Select: Determines the data sent on GPIO2 for the port back channel. 0xxx: Pin GPIOx where x is BC_GPIO2_SEL[2:0] 1000: Constant value of 0 1001: Constant value of 1 1010: FrameSync signal 1011 - 1111: Reserved

7.6.1.99 RAW10_ID Register (Address = 0x70) [Reset = 0x2B]

RAW10_ID is shown in Table 7-120.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands. RAW10 virtual channel mapping only applies when V3Link is operating in RAW10 input mode. See register 0x71 for RAW12 and register 0x72 for CSI-2 mode operation.

Table 7-120 RAW10_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RAW10_VC	R/W	0x0	RAW10 Mode Virtual Channel This field configures the CSI-2 Virtual Channel assigned to the port when receiving RAW10 data. The field value defaults to the V3Link receive port number (0, 1, 2, or 3)
5:0	RAW10_DT	R/W	0x2B	RAW10 DT This field configures the CSI-2 data type used in RAW10 mode. The default of 0x2B matches the CSI-2 specification.

7.6.1.100 RAW12_ID Register (Address = 0x71) [Reset = 0x2C]

RAW12_ID is shown in Table 7-121.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands. RAW12 virtual channel mapping only applies when V3Link is operating in RAW12 input mode. See register 0x70 for RAW10 and register 0x72 for CSI-2 mode operation.

Table 7-121 RAW12_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RAW12_VC	R/W	0x0	RAW12 Mode Virtual Channel This field configures the CSI-2 Virtual Channel assigned to the port when receiving RAW12 data. The field value defaults to the V3Link receive port number (0, 1, 2, or 3)
5:0	RAW12_DT	R/W	0x2C	RAW12 DT This field configures the CSI-2 data type used in RAW12 mode. The default of 0x2C matches the CSI-2 specification.

7.6.1.101 CSI_VC_MAP Register (Address = 0x72) [Reset = 0xE4]

CSI_VC_MAP is shown in Table 7-122.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands. CSI-2 virtual channel mapping only applies when V3Link operating in CSI-2 input mode. See registers 0x70 and 0x71 for RAW mode operation.

Table 7-122 CSI_VC_MAP Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CSI_VC_MAP	R/W	0xE4	CSI-2 Virtual Channel Mapping Register This register provides a method for replacing the Virtual Channel Identifier (VC-ID) of incoming CSI-2 packets. [7:6]: Map value for VC-ID of 3 [5:4]: Map value for VC-ID of 2 [3:2]: Map value for VC-ID of 1 [1:0]: Map value for VC-ID of 0

7.6.1.102 LINE_COUNT_1 Register (Address = 0x73) [Reset = 0x00]

LINE_COUNT_1 is shown in Table 7-123.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-123 LINE_COUNT_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	LINE_COUNT_HI	R	0x0	High byte of Line Count The Line Count reports the line count for the most recent video frame. When interrupts are enabled for the Line Count (via the IE_LINE_CNT_CHG register bit), the Line Count value is frozen until read.

7.6.1.103 LINE_COUNT_0 Register (Address = 0x74) [Reset = 0x00]

LINE_COUNT_0 is shown in Table 7-124.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-124 LINE_COUNT_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	LINE_COUNT_LO	R	0x0	Low byte of Line Count The Line Count reports the line count for the most recent video frame. When interrupts are enabled for the Line Count (via the IE_LINE_CNT_CHG register bit), the Line Count value is frozen until read. In addition, when reading the LINE_COUNT registers, the LINE_COUNT_LO is latched upon reading LINE_COUNT_HI to ensure consistency between the two portions of the Line Count.

7.6.1.104 LINE_LEN_1 Register (Address = 0x75) [Reset = 0x00]

LINE_LEN_1 is shown in Table 7-125.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-125 LINE_LEN_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	LINE_LEN_HI	R	0x0	High byte of Line Length The Line Length reports the line length recorded during the most recent video frame. If line length is not stable during the frame, this register will report the length of the last line in the video frame. When interrupts are enabled for the Line Length (via the IE_LINE_LEN_CHG register bit), the Line Length value is frozen until read.

7.6.1.105 LINE_LEN_0 Register (Address = 0x76) [Reset = 0x00]

LINE_LEN_0 is shown in Table 7-126.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-126 LINE_LEN_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	LINE_LEN_LO	R	0x0	Low byte of Line Length The Line Length reports the length of the most recent video line. When interrupts are enabled for the Line Length (via the IE_LINE_LEN_CHG register bit), the Line Length value is frozen until read. In addition, when reading the LINE_LEN registers, the LINE_LEN_LO is latched upon reading LINE_LEN_HI to ensure consistency between the two portions of the Line Length.

7.6.1.106 FREQ_DET_CTL Register (Address = 0x77) [Reset = 0xC5]

FREQ_DET_CTL is shown in Table 7-127.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-127 FREQ_DET_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	FREQ_HYST	R/W	0x3	Frequency Detect Hysteresis The Frequency detect hysteresis setting allows ignoring minor fluctuations in frequency. A new frequency measurement will be captured only if the measured frequency differs from the current measured frequency by more than the FREQ_HYST setting. The FREQ_HYST setting is in MHz.
5:4	FREQ_STABLE_THR	R/W	0x0	Frequency Stable Threshold The Frequency detect circuit can be used to detect a stable clock frequency. The Stability Threshold determines the amount of time required for the clock frequency to stay within the FREQ_HYST range to be considered stable: 00: 40us 01: 80us 10: 320us 11: 1.28ms
3:0	FREQ_LO_THR	R/W	0x5	Frequency Low Threshold Sets the low threshold for the Clock frequency detect circuit in MHz. If the input clock is below this threshold, the NO_V3LINK_CLK status will be set to 1.

7.6.1.107 MAILBOX_0 Register (Address = 0x78) [Reset = 0x00]

MAILBOX_0 is shown in Table 7-128.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-128 MAILBOX_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	MAILBOX_0	R/W	0x0	Mailbox Register This register is an unused read/write register that can be used for any purpose such as passing messages between I2C controllers on opposite ends of the link.

7.6.1.108 MAILBOX_1 Register (Address = 0x79) [Reset = 0x01]

MAILBOX_1 is shown in Table 7-129.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-129 MAILBOX_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	MAILBOX_1	R/W	0x1	Mailbox Register This register is an unused read/write register that can be used for any purpose such as passing messages between I2C controllers on opposite ends of the link.

7.6.1.109 CSI_RX_STS Register (Address = 0x7A) [Reset = 0x00]

CSI_RX_STS is shown in Table 7-130.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-130 CSI_RX_STS Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0x0	Reserved
3	LENGTH_ERR	RC	0x0	Packet Length Error detected for received CSI-2 packet If set, this bit indicates a packet length error was detected on at least one CSI-2 packet received from the camera. Packet length errors occur if the data length field in the packet header does not match the actual data length for the packet. 1: One or more Packet Length errors have been detected 0: No Packet Length errors have been detected This bit is cleared on read.
2	CKSUM_ERR	RC	0x0	Data Checksum Error detected for received CSI-2 packet If set, this bit indicates a data checksum error was detected on at least one CSI-2 packet received from the camera. Data checksum errors indicate an error was detected in the packet data portion of the CSI-2 packet. 1: One or more Data Checksum errors have been detected 0: No Data Checksum errors have been detected This bit is cleared on read.
1	ECC2_ERR	RC	0x0	2-bit ECC Error detected for received CSI-2 packet If set, this bit indicates a multi-bit ECC error was detected on at least one CSI-2 packet received from the camera. Multi-bit errors are not corrected by the device. 1: One or more multi-bit ECC errors have been detected 0: No multi-bit ECC errors have been detected This bit is cleared on read.
0	ECC1_ERR	RC	0x0	1-bit ECC Error detected for received CSI packet If set, this bit indicates a single-bit ECC error was detected on at least one CSI packet received from the camera. Single-bit errors are corrected by the device. 1: One or more 1-bit ECC errors have been detected 0: No 1-bit ECC errors have been detected This bit is cleared on read.

7.6.1.110 CSI_ERR_COUNTER Register (Address = 0x7B) [Reset = 0x00]

CSI_ERR_COUNTER is shown in Table 7-131.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-131 CSI_ERR_COUNTER Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CSI_ERR_CNT	RC	0x0	CSI Error Counter Register This register counts the number of CSI-2 packets received with errors since the last read of the counter.

7.6.1.111 PORT_CONFIG2 Register (Address = 0x7C) [Reset = 0x20]

PORT_CONFIG2 is shown in Table 7-132.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-132 PORT_CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RAW10_8BIT_CTL	R/W	0x0	Raw10 8-bit mode When Raw10 Mode is enabled for the port, the input data is processed as 8-bit data and packed accordingly for transmission over CSI. 00: Normal Raw10 Mode 01: Reserved 10: 8-bit processing using upper 8 bits 11: 8-bit processing using lower 8 bits
5	DISCARD_ON_PAR_ERR	R/W	0x1	Discard frames on Parity Error 0: Forward packets with parity errors 1: Truncate Frames if a parity error is detected
4	DISCARD_ON_LINE_SIZE	R/W	0x0	Discard frames on Line Size 0: Allow changes in Line Size within packets 1: Truncate Frames if a change in line size is detected
3	DISCARD_ON_FRAME_SIZE	R/W	0x0	Discard frames on change in Frame Size When enabled, a change in the number of lines in a frame will result in truncation of the packet. The device will resume forwarding video frames based on the PASS_THRESHOLD setting in the PORT_PASS_CTL register. 0: Allow changes in Frame Size 1: Truncate Frames if a change in frame size is detected
2	AUTO_POLARITY	R/W	0x0	Automatic Polarity Detection This register enables automatic polarity detection. When this bit is set, polarity of LineValid and FrameValid will be automatically detected from the incoming data. In this mode, at least one initial frame will be discarded to allow for proper detection of the incoming video. 1: Automatically detect LV and FV polarity 0: Use LV_POLARITY and FV_POLARITY register settings to determine polarity
1	LV_POLARITY	R/W	0x0	LineValid Polarity This register indicates the expected polarity for the LineValid indication received in Raw mode. 1: LineValid is low for the duration of the video frame 0: LineValid is high for the duration of the video frame
0	FV_POLARITY	R/W	0x0	FrameValid Polarity This register indicates the expected polarity for the FrameValid indication received in Raw mode. 1: FrameValid is low for the duration of the video frame 0: FrameValid is high for the duration of the video frame

7.6.1.112 PORT_PASS_CTL Register (Address = 0x7D) [Reset = 0x00]

PORT_PASS_CTL is shown in Table 7-133.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-133 PORT_PASS_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PASS_DISCARD_EN	R/W	0x0	Pass Discard Enable Discard packets if PASS is not indicated. 0: Ignore PASS for forwarding packets 1: Discard packets when PASS is not true
6	PASS_CLEAR_CNT	R/W	0x0	Pass Clear Count Control This bit controls the values read back from the LINE_COUNT_1, LINE_COUNT_0, LINE_LEN_1, and LINE_LEN_0 registers. 0: Registers read back the counter vaues regardless of the state of the PASS flag 1: Registers read back zero when the PASS flag is de-asserted and the count values when PASS is asserted
5	PASS_LINE_CNT	R/W	0x0	Pass Line Count Control This register controls whether the device will include line count in qualification of the Pass indication: 0: Don't check line count 1: Check line count When checking line count, Pass is deasserted upon detection of a change in the number of video lines per frame. Pass will not be reasserted until the PASS_THRESHOLD setting is met.
4	PASS_LINE_SIZE	R/W	0x0	Pass Line Size Control This register controls whether the device will include line size in qualification of the Pass indication: 0: Don't check line size 1: Check line size When checking line size, Pass is deasserted upon detection of a change in video line size. Pass will not be reasserted until the PASS_THRESHOLD setting is met.
3	PASS_PARITY_ERR	R/W	0x0	Parity Error Mode If this bit is set to 0, the port Pass indication is deasserted for every parity error detected on the V3LINK Receive interface. If this bit is set to a 1, the port Pass indication is cleared on a parity error and remain clear until the PASS_THRESHOLD is met.
2	PASS_WDOG_DIS	R/W	0x0	RX Port Pass Watchdog disable When enabled, if the V3LINK Receiver does not detect a valid frame end condition within two video frame periods, the Pass indication is deasserted. The watchdog timer will not have any effect if the PASS_THRESHOLD is set to 0. 0: Enable watchdog timer for RX Pass 1: Disable watchdog timer for RX Pass
1:0	PASS_THRESHOLD	R/W	0x0	Pass Threshold Register This register controls the number of valid frames before asserting the port Pass indication. If set to 0, PASS is asserted after Receiver Lock detect. If non-zero, PASS is asserted following reception of the programmed number of valid frames.

7.6.1.113 SEN_INT_RISE_CTL Register (Address = 0x7E) [Reset = 0x00]

SEN_INT_RISE_CTL is shown in Table 7-134.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-134 SEN_INT_RISE_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	SEN_INT_RISE_MASK	R/W	0x0	Sensor Interrupt Rise Mask This register provides the interrupt mask for detecting rising edge transitions on the bits in SENSOR_STS_0. If a mask bit is set in this register, a rising edge transition on the corresponding SENSOR_STS_0 bit will generate an interrupt that will be latched in the SEN_INT_RISE_STS register.

7.6.1.114 SEN_INT_FALL_CTL Register (Address = 0x7F) [Reset = 0x00]

SEN_INT_FALL_CTL is shown in Table 7-135.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-135 SEN_INT_FALL_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	SEN_INT_FALL_MASK	R/W	0x0	Sensor Interrupt Fall Mask This register provides the interrupt mask for detecting falling edge transitions on the bits in SENSOR_STS_0. If a mask bit is set in this register, a falling edge transition on the corresponding SENSOR_STS_0 bit will generate an interrupt that will be latched in the SEN_INT_FALL_STS register.

7.6.1.115 CSI0_FRAME_COUNT_HI Register (Address = 0x90) [Reset = 0x00]

CSI0_FRAME_COUNT_HI is shown in Table 7-136.

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Table 7-136 CSI0_FRAME_COUNT_HI Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CSI0_FRAME_COUNT_HI	RC	0x0	CSI-2 Port 0, Frame Counter MSBs When read, this register returns the value of bits [15:8] of the 16-bit counter CSI0_FRAME_COUNT. The LSBs of the counter are sampled into the CSI0_FRAME_COUNT_LO register and the counter is cleared.

7.6.1.116 CSI0_FRAME_COUNT_LO Register (Address = 0x91) [Reset = 0x00]

CSI0_FRAME_COUNT_LO is shown in Table 7-137.

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Table 7-137 CSI0_FRAME_COUNT_LO Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CSI0_FRAME_COUNT_LO	R	0x0	CSI-2 Port 0, Frame Counter LSBs When read, this register returns the value of bits [7:0] of the 16-bit counter CSI0_FRAME_COUNT. The CSI0_FRAME_COUNT_HI register must be read first to snapshot the LSBs of the counter into this register.

7.6.1.117 CSI0_FRAME_ERR_COUNT_HI Register (Address = 0x92) [Reset = 0x00]

CSI0_FRAME_ERR_COUNT_HI is shown in Table 7-138.

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Table 7-138 CSI0_FRAME_ERR_COUNT_HI Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CSI0_FRAME_ERR_COUNT_HI	RC	0x0	CSI-2 Port 0, Frame Counter with Errors MSBs When read, this register returns the value of bits [15:8] of the 16-bit counter CSI0_FRAME_ERR_COUNT. The LSBs of the counter are sampled into the CSI0_FRAME_ERR_COUNT_LO register and the counter is cleared.

7.6.1.118 CSI0_FRAME_ERR_COUNT_LO Register (Address = 0x93) [Reset = 0x00]

CSI0_FRAME_ERR_COUNT_LO is shown in Table 7-139.

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Table 7-139 CSI0_FRAME_ERR_COUNT_LO Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CSI0_FRAME_ERR_COUNT_LO	R	0x0	CSI-2 Port 0, Frame Counter with Errors LSBs When read, this register returns the value of bits [7:0] of the 16-bit counter CSI0_FRAME_ERR_COUNT. The CSI0_FRAME_ERR_COUNT_HI register must be read first to snapshot the LSBs of the counter into this register.

7.6.1.119 CSI0_LINE_COUNT_HI Register (Address = 0x94) [Reset = 0x00]

CSI0_LINE_COUNT_HI is shown in Table 7-140.

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Table 7-140 CSI0_LINE_COUNT_HI Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CSI0_LINE_COUNT_HI	RC	0x0	CSI-2 Port 0, Line Counter MSBs When read, this register returns the value of bits [15:8] of the 16-bit counter CSI0_LINE_COUNT. The LSBs of the counter are sampled into the CSI0_LINE_COUNT_LO register and the counter is cleared.

7.6.1.120 CSI0_LINE_COUNT_LO Register (Address = 0x95) [Reset = 0x00]

CSI0_LINE_COUNT_LO is shown in Table 7-141.

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Table 7-141 CSI0_LINE_COUNT_LO Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CSI0_LINE_COUNT_LO	R	0x0	CSI-2 Port 0, Line Counter LSBs When read, this register returns the value of bits [7:0] of the 16-bit counter CSI0_LINE_COUNT. The CSI0_LINE_COUNT_HI register must be read first to snapshot the LSBs of the counter into this register.

7.6.1.121 CSI0_LINE_ERR_COUNT_HI Register (Address = 0x96) [Reset = 0x00]

CSI0_LINE_ERR_COUNT_HI is shown in Table 7-142.

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Table 7-142 CSI0_LINE_ERR_COUNT_HI Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CSI0_LINE_ERR_COUNT_HI	RC	0x0	CSI-2 Port 0, Line Counter with Errors MSBs When read, this register returns the value of bits [15:8] of the 16-bit counter CSI0_LINE_ERR_COUNT. The LSBs of the counter are sampled into the CSI0_LINE_ERR_COUNT_LO register and the counter is cleared.

7.6.1.122 CSI0_LINE_ERR_COUNT_LO Register (Address = 0x97) [Reset = 0x00]

CSI0_LINE_ERR_COUNT_LO is shown in Table 7-143.

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Table 7-143 CSI0_LINE_ERR_COUNT_LO Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CSI0_LINE_ERR_COUNT_LO	R	0x0	CSI-2 Port 0, Line Counter with Errors LSBs When read, this register returns the value of bits [7:0] of the 16-bit counter CSI0_LINE_ERR_COUNT. The CSI0_LINE_ERR_COUNT_HI register must be read first to snapshot the LSBs of the counter into this register.

7.6.1.123 CSI1_FRAME_COUNT_HI Register (Address = 0x98) [Reset = 0x00]

CSI1_FRAME_COUNT_HI is shown in Table 7-144.

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Table 7-144 CSI1_FRAME_COUNT_HI Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CSI1_FRAME_COUNT_HI	RC	0x0	CSI-2 Port 1, Frame Counter MSBs When read, this register returns the value of bits [15:8] of the 16-bit counter CSI1_FRAME_COUNT. The LSBs of the counter are sampled into the CSI1_FRAME_COUNT_LO register and the counter is cleared.

7.6.1.124 CSI1_FRAME_COUNT_LO Register (Address = 0x99) [Reset = 0x00]

CSI1_FRAME_COUNT_LO is shown in Table 7-145.

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Table 7-145 CSI1_FRAME_COUNT_LO Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CSI1_FRAME_COUNT_LO	R	0x0	CSI-2 Port 1, Frame Counter LSBs When read, this register returns the value of bits [7:0] of the 16-bit counter CSI1_FRAME_COUNT. The CSI1_FRAME_COUNT_HI register must be read first to snapshot the LSBs of the counter into this register.

7.6.1.125 CSI1_FRAME_ERR_COUNT_HI Register (Address = 0x9A) [Reset = 0x00]

CSI1_FRAME_ERR_COUNT_HI is shown in Table 7-146.

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Table 7-146 CSI1_FRAME_ERR_COUNT_HI Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CSI1_FRAME_ERR_COUNT_HI	RC	0x0	CSI-2 Port 1, Frame Counter with Errors MSBs When read, this register returns the value of bits [15:8] of the 16-bit counter CSI1_FRAME_ERR_COUNT. The LSBs of the counter are sampled into the CSI1_FRAME_ERR_COUNT_LO register and the counter is cleared.

7.6.1.126 CSI1_FRAME_ERR_COUNT_LO Register (Address = 0x9B) [Reset = 0x00]

CSI1_FRAME_ERR_COUNT_LO is shown in Table 7-147.

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Table 7-147 CSI1_FRAME_ERR_COUNT_LO Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CSI1_FRAME_ERR_COUNT_LO	R	0x0	CSI-2 Port 1, Frame Counter with Errors LSBs When read, this register returns the value of bits [7:0] of the 16-bit counter CSI1_FRAME_ERR_COUNT. The CSI1_FRAME_ERR_COUNT_HI register must be read first to snapshot the LSBs of the counter into this register.

7.6.1.127 CSI1_LINE_COUNT_HI Register (Address = 0x9C) [Reset = 0x00]

CSI1_LINE_COUNT_HI is shown in Table 7-148.

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Table 7-148 CSI1_LINE_COUNT_HI Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CSI1_LINE_COUNT_HI	RC	0x0	CSI-2 Port 1, Line Counter MSBs When read, this register returns the value of bits [15:8] of the 16-bit counter CSI1_LINE_COUNT. The LSBs of the counter are sampled into the CSI1_LINE_COUNT_LO register and the counter is cleared.

7.6.1.128 CSI1_LINE_COUNT_LO Register (Address = 0x9D) [Reset = 0x00]

CSI1_LINE_COUNT_LO is shown in Table 7-149.

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Table 7-149 CSI1_LINE_COUNT_LO Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CSI1_LINE_COUNT_LO	R	0x0	CSI-2 Port 1, Line Counter LSBs When read, this register returns the value of bits [7:0] of the 16-bit counter CSI1_LINE_COUNT. The CSI1_LINE_COUNT_HI register must be read first to snapshot the LSBs of the counter into this register.

7.6.1.129 CSI1_LINE_ERR_COUNT_HI Register (Address = 0x9E) [Reset = 0x00]

CSI1_LINE_ERR_COUNT_HI is shown in Table 7-150.

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Table 7-150 CSI1_LINE_ERR_COUNT_HI Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CSI1_LINE_ERR_COUNT_HI	RC	0x0	CSI-2 Port 1, Line Counter with Errors MSBs When read, this register returns the value of bits [15:8] of the 16-bit counter CSI1_LINE_ERR_COUNT. The LSBs of the counter are sampled into the CSI1_LINE_ERR_COUNT_LO register and the counter is cleared.

7.6.1.130 CSI1_LINE_ERR_COUNT_LO Register (Address = 0x9F) [Reset = 0x00]

CSI1_LINE_ERR_COUNT_LO is shown in Table 7-151.

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Table 7-151 CSI1_LINE_ERR_COUNT_LO Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CSI1_LINE_ERR_COUNT_LO	R	0x0	CSI-2 Port 1, Line Counter with Errors LSBs When read, this register returns the value of bits [7:0] of the 16-bit counter CSI1_LINE_ERR_COUNT. The CSI1_LINE_ERR_COUNT_HI register must be read first to snapshot the LSBs of the counter into this register.

7.6.1.131 REFCLK_FREQ Register (Address = 0xA5) [Reset = 0x00]

REFCLK_FREQ is shown in Table 7-152.

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Table 7-152 REFCLK_FREQ Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	REFCLK_FREQ	R	0x0	REFCLK frequency measurement in MHz.

7.6.1.132 IND_ACC_CTL Register (Address = 0xB0) [Reset = 0x1C]

IND_ACC_CTL is shown in Table 7-153.

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Table 7-153 IND_ACC_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0x0	Reserved
5:2	IA_SEL	R/W	0x7	Indirect Access Register Select: Selects target for register access 0000: Pattern Generator and CSI-2 Timing (PATGEN_AND_CSI-2) Registers xxxx: RESERVED
1	IA_AUTO_INC	R/W	0x0	Indirect Access Auto Increment: Enables auto-increment mode. Upon completion of a read or write, the register address will automatically be incremented by 1
0	IA_READ	R/W	0x0	Indirect Access Read: Setting this allows generation of a read strobe to the selected register block upon setting of the IND_ACC_ADDR register. In auto-increment mode, read strobes will also be asserted following a read of the IND_ACC_DATA register. This function is only required for blocks that need to pre-fetch register data.

7.6.1.133 IND_ACC_ADDR Register (Address = 0xB1) [Reset = 0x3A]

IND_ACC_ADDR is shown in Table 7-154.

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Table 7-154 IND_ACC_ADDR Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	IA_ADDR	R/W	0x3A	Indirect Access Register Offset: This register contains the 8-bit register offset for the indirect access.

7.6.1.134 IND_ACC_DATA Register (Address = 0xB2) [Reset = 0x14]

IND_ACC_DATA is shown in Table 7-155.

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Table 7-155 IND_ACC_DATA Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	IA_DATA	R/W	0x14	Indirect Access Data: Writing this register will cause an indirect write of the IND_ACC_DATA value to the selected analog block register. Reading this register will return the value of the selected block register. The default value may be different from a device to a device.

7.6.1.135 BIST_CTL Register (Address = 0xB3) [Reset = 0x08]

BIST_CTL is shown in Table 7-156.

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Table 7-156 BIST_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	BIST_OUT_MODE	R/W	0x0	BIST Output Mode 00: No toggling 01: Alternating 1/0 toggling 1x: Toggle based on BIST data
5:4	RESERVED	R	0x0	Reserved
3	RESERVED	R	0x0	Bist Configuration 1: Reserved 0: Bist configured through bits 2:0 in this register
2:1	BIST_CLOCK_SOURCE	R/W	0x0	BIST Clock Source This register field selects the BIST Clock Source at the Serializer. These register bits are automatically written to the CLOCK SOURCE bits (register offset 0x14) in the Serializer after BIST is enabled. See the appropriate Serializer register descriptions for details.
0	BIST_EN	R/W	0x0	BIST Control 1: Enabled 0: Disabled

7.6.1.136 PAR_ERR_CTRL Register (Address = 0xB6) [Reset = 0x18]

PAR_ERR_CTRL is shown in Table 7-157.

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Table 7-157 PAR_ERR_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved
6	RESERVED	R	0x0	Reserved
5	PAR_ERR_CNTR_MODE	R/W	0x0	Parity Error Counter Mode 0: Clear Parity Error counter if receiver is not locked 1: Maintain Parity Error count value through loss of lock
4	DIS_LINK_PAR	R/W	0x1	Disable checking of Parity Errors when checking for V3Link Lock 0: Parity errors will prevent assertion of forward channel lock detect (RX Lock). 1: Parity errors will NOT prevent assertion of forward channel lock detect (RX Lock). This is the default mode of the device.
3	DIS_LINKLOSS_PAR	R/W	0x1	Disable checking of Parity Errors when checking for loss of link 0: Parity errors will result in loss of forward channel lock detect (RX Lock). 1: Parity errors will NOT result in loss of forward channel lock detect (RX Lock). This is the default mode of the device.
2	RESERVED	R	0x0	Reserved
1	RESERVED	R	0x0	Reserved
0	RESERVED	R	0x0	Reserved

7.6.1.137 MODE_IDX_STS Register (Address = 0xB8) [Reset = 0xXX]

MODE_IDX_STS is shown in Table 7-158.

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Table 7-158 MODE_IDX_STS Register Field Descriptions

Bit	Field	Type	Reset	Description
7	IDX_DONE	R	0x1	IDX Done If set, indicates the IDX decode has completed and latched into the IDX status bits.
6:4	IDX	R	invalid	IDX Decode (Strap) 3-bit decode from IDX pin
3	MODE_DONE	R	0x1	MODE Done: If set, indicates the MODE decode has completed and latched into the MODE status bits.
2:0	MODE	R	invalid	MODE Decode (Strap) 3-bit decode from MODE pin

7.6.1.138 LINK_ERROR_COUNT Register (Address = 0xB9) [Reset = 0x33]

LINK_ERROR_COUNT is shown in Table 7-159.

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Table 7-159 LINK_ERROR_COUNT Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0x0	Reserved
5	LINK_SFIL_WAIT	R/W	0x1	During SFILTER adaption, setting this bit will cause the Lock detect circuit to ignore errors during the SFILTER wait period after the SFILTER control is updated. 1: Errors during SFILTER Wait period will be ignored 0: Errors during SFILTER Wait period will not be ignored and may cause loss of Lock
4	LINK_ERR_COUNT_EN	R/W	0x1	Enable serial link data integrity error count 1: Enable error count 0: DISABLE
3:0	LINK_ERR_THRESH	R/W	0x3	Link error count threshold. The Link Error Counter monitors the forward channel link and determines when lock will be dropped. If the error counter is enabled, the deserializer will lose lock once the error counter reaches the LINK_ERR_THRESH value. If the link error counter is disabled, the deserializer will lose lock after one error. The control bits in the PAR_ERR_CTRL register can be used to enable error conditions individually.

7.6.1.139 V3LINK_ENC_CTL Register (Address = 0xBA) [Reset = 0x83]

V3LINK_ENC_CTL is shown in Table 7-160.

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Recommended to set bit seven in the V3Link encoder control register to 0 in order to prevent any updates of link information values from encoded packets that do not pass CRC check. The V3Link Encoder CRC flag must also be in place by setting V3LINK_ENC_CRC_DIS (register 0x4A[4]) to 1.

Table 7-160 V3LINK_ENC_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	0: Enable V3Link encoder CRC (recommended) 1: Disable V3Link encoder CRC
6:0	RESERVED	R	0x0	Reserved

7.6.1.140 FV_MIN_TIME Register (Address = 0xBC) [Reset = 0x80]

FV_MIN_TIME is shown in Table 7-161.

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Table 7-161 FV_MIN_TIME Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	FRAME_VALID_MIN	R/W	0x80	Frame Valid Minimum Time This register controls the minimum time the FrameValid (FV) should be active before the Raw mode V3LINK receiver generates a FrameStart packet. Duration is in V3LINK clock periods.

7.6.1.141 GPIO_PD_CTL Register (Address = 0xBE) [Reset = 0x00]

GPIO_PD_CTL is shown in Table 7-162.

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Table 7-162 GPIO_PD_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	GPIO7_PD_DIS	R/W	0x0	GPIO7 Pull-down Resistor Disable: The GPIO pins by default include a pulldown resistor (25-kΩ typ) that is automatically enabled when the GPIO is not in an output mode. When this bit is set, the pulldown resistor will also be disabled when the GPIO pin is in an input only mode. 1: Disable GPIO pull-down resistor 0: Enable GPIO pull-down resistor
6	GPIO6_PD_DIS	R/W	0x0	GPIO6 Pull-down Resistor Disable: The GPIO pins by default include a pulldown resistor (25-kΩ typ) that is automatically enabled when the GPIO is not in an output mode. When this bit is set, the pulldown resistor will also be disabled when the GPIO pin is in an input only mode. 1: Disable GPIO pull-down resistor 0: Enable GPIO pull-down resistor
5	GPIO5_PD_DIS	R/W	0x0	GPIO5 Pull-down Resistor Disable: The GPIO pins by default include a pulldown resistor (25-kΩ typ) that is automatically enabled when the GPIO is not in an output mode. When this bit is set, the pulldown resistor will also be disabled when the GPIO pin is in an input only mode. 1: Disable GPIO pull-down resistor 0: Enable GPIO pull-down resistor
4	GPIO4_PD_DIS	R/W	0x0	GPIO4 Pull-down Resistor Disable: The GPIO pins by default include a pulldown resistor (25-kΩ typ) that is automatically enabled when the GPIO is not in an output mode. When this bit is set, the pulldown resistor will also be disabled when the GPIO pin is in an input only mode. 1: Disable GPIO pull-down resistor 0: Enable GPIO pull-down resistor
3	GPIO3_PD_DIS	R/W	0x0	GPIO3 Pull-down Resistor Disable: The GPIO pins by default include a pulldown resistor (25-kΩ typ) that is automatically enabled when the GPIO is not in an output mode. When this bit is set, the pulldown resistor will also be disabled when the GPIO pin is in an input only mode. 1: Disable GPIO pull-down resistor 0: Enable GPIO pull-down resistor
2	GPIO2_PD_DIS	R/W	0x0	GPIO2 Pull-down Resistor Disable: The GPIO pins by default include a pulldown resistor (25-kΩ typ) that is automatically enabled when the GPIO is not in an output mode. When this bit is set, the pulldown resistor will also be disabled when the GPIO pin is in an input only mode. 1: Disable GPIO pull-down resistor 0: Enable GPIO pull-down resistor
1	GPIO1_PD_DIS	R/W	0x0	GPIO1 Pull-down Resistor Disable: The GPIO pins by default include a pulldown resistor (25-kΩ typ) that is automatically enabled when the GPIO is not in an output mode. When this bit is set, the pulldown resistor will also be disabled when the GPIO pin is in an input only mode. 1: Disable GPIO pull-down resistor 0: Enable GPIO pull-down resistor
0	GPIO0_PD_DIS	R/W	0x0	GPIO0 Pull-down Resistor Disable: The GPIO pins by default include a pulldown resistor (25-kΩ typ) that is automatically enabled when the GPIO is not in an output mode. When this bit is set, the pulldown resistor will also be disabled when the GPIO pin is in an input only mode. 1: Disable GPIO pull-down resistor 0: Enable GPIO pull-down resistor

7.6.1.142 PORT_DEBUG Register (Address = 0xD0) [Reset = 0x00]

PORT_DEBUG is shown in Table 7-163.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-163 PORT_DEBUG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved
6	RESERVED	R	0x0	Reserved
5	SER_BIST_ACT	R	0x0	Serializer BIST active This register indicates the Serializer is in BIST mode. If the Deserializer is not in BIST mode, this could indicate an error condition.
4:2	RESERVED	R	0x0	Reserved
1	FORCE_BC_ERRORS	R/W	0x0	This bit indroduces continuous errors into Back channel frame.
0	FORCE_1_BC_ERROR	RH/W1S	0x0	This bit indroduces one error into Back channel frame. Self clearing bit.

7.6.1.143 AEQ_CTL2 Register (Address = 0xD2) [Reset = 0x94]

AEQ_CTL2 is shown in Table 7-164.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-164 AEQ_CTL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	ADAPTIVE_EQ_RELOCK_TIME	R/W	0x4	Time to wait for lock before incrementing the EQ to next setting 000: 164 us 001: 328 us 010: 655 us 011: 1.31 ms 100: 2.62 ms 101: 5.24 ms 110: 10.5ms 111: 21.0 ms
4	AEQ_1ST_LOCK_MODE	R/W	0x1	AEQ First Lock Mode This register bit controls the Adaptive Equalizer algorithm operation at initial Receiver Lock. 0: Initial AEQ lock may occur at any value 1: Initial Receiver lock will restart AEQ at 0, providing a more deterministic initial AEQ value
3	AEQ_RESTART	RH/W1S	0x0	Set high to restart AEQ adaptation from initial value. This bit is self clearing. Adaption is restarted.
2	SET_AEQ_FLOOR	R/W	0x1	AEQ adaptation starts from a pre-set floor value rather than from zero - good in long cable situations
1:0	RESERVED	R	0x0	Reserved

7.6.1.144 AEQ_STATUS Register (Address = 0xD3) [Reset = 0x00]

AEQ_STATUS is shown in Table 7-165.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-165 AEQ_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0x0	Reserved
5:3	EQ_STATUS_2	R	0x0	Adaptive EQ Status 2
2:0	EQ_STATUS_1	R	0x0	Adaptive EQ Status 1

7.6.1.145 ADAPTIVE_EQ_BYPASS Register (Address = 0xD4) [Reset = 0x60]

ADAPTIVE_EQ_BYPASS is shown in Table 7-166.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-166 ADAPTIVE_EQ_BYPASS Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	EQ_STAGE_1_SELECT_VALUE	R/W	0x3	EQ select value[5:3] - Used if adaptive EQ is bypassed.
4	AEQ_LOCK_MODE	R/W	0x0	Adaptive Equalizer lock mode When set to a 1, Receiver Lock status requires the Adaptive Equalizer to complete adaption. When set to a 0, Receiver Lock is based only on the Lock circuit itself. AEQ may not have stabilized.
3:1	EQ_STAGE_2_SELECT_VALUE	R/W	0x0	EQ select value [2:0] - Used if adaptive EQ is bypassed.
0	ADAPTIVE_EQ_BYPASS	R/W	0x0	1: Disable adaptive EQ 0: Enable adaptive EQ

7.6.1.146 AEQ_MIN_MAX Register (Address = 0xD5) [Reset = 0xF2]

AEQ_MIN_MAX is shown in Table 7-167.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-167 AEQ_MIN_MAX Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	AEQ_MAX	R/W	0xF	Adaptive Equalizer Maximum value This register sets the maximum value for the Adaptive EQ algorithm.
3:0	ADAPTIVE_EQ_FLOOR_VALUE	R/W	0x2	When AEQ floor is enabled by register 0xD2[2] the starting setting is given by this register.

7.6.1.147 SFILTER_STS_0 Register (Address = 0xD6) [Reset = 0x00]

SFILTER_STS_0 is shown in Table 7-168.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-168 SFILTER_STS_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SFILTER_MAXED	RC	0x0	SFILTER has reached limit When set, the adaptive control of the SFILTER has reached the maximum limit and the algorithm is unable to further adapt. This register is cleared on read.
6	SFILTER_STABLE	R	0x0	Indicates SFILTER setting is stable This register bit value is latched low. Read to clear for current status.
5:0	SFILTER_CDLY	R	0x0	SFITLER Clock Delay Current value of clock delay control to SFILTER circuit

7.6.1.148 SFILTER_STS_1 Register (Address = 0xD7) [Reset = 0x00]

SFILTER_STS_1 is shown in Table 7-169.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-169 SFILTER_STS_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved
6	SFILTER_ERROR	RC	0x0	SFILTER measurement error detect If this bit is set, one or more measurements since the last read reported invalid results. This register is cleared on read.
5:0	SFILTER_DDLY	R	0x0	SFITLER Data Delay Current value of data delay control to SFILTER circuit (The readout may vary depending on device status).

7.6.1.149 PORT_ICR_HI Register (Address = 0xD8) [Reset = 0x00]

PORT_ICR_HI is shown in Table 7-170.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-170 PORT_ICR_HI Register Field Descriptions

Bit	Field	Type	Reset	Description
7:3	RESERVED	R	0x0	Reserved
2	IE_V3LINK_ENC_ERR	R/W	0x0	Interrupt on V3Link Receiver Encoding Error When enabled, an interrupt is generated on detection of an encoding error on the V3Link interface for the receive port as reported in the V3LINK_ENC_ERROR bit in the RX_PORT_STS2 register
1	IE_BCC_SEQ_ERR	R/W	0x0	Interrupt on BCC SEQ Sequence Error When enabled, an interrupt is generated if a Sequence Error is detected for the Bi-directional Control Channel forward channel receiver as reported in the BCC_SEQ_ERROR bit in the RX_PORT_STS1 register.
0	IE_BCC_CRC_ERR	R/W	0x0	Interrupt on BCC CRC error detect When enabled, an interrupt is generated if a CRC error is detected on a Bi-directional Control Channel frame received over the V3Link forward channel as reported in the BCC_CRC_ERROR bit in the RX_PORT_STS1 register.

7.6.1.150 PORT_ICR_LO Register (Address = 0xD9) [Reset = 0x00]

PORT_ICR_LO is shown in Table 7-171.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-171 PORT_ICR_LO Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved
6	IE_LINE_LEN_CHG	R/W	0x0	Interrupt on Video Line length When enabled, an interrupt is generated if the length of the video line changes. Status is reported in the LINE_LEN_CHG bit in the RX_PORT_STS2 register.
5	IE_LINE_CNT_CHG	R/W	0x0	Interrupt on Video Line count When enabled, an interrupt is generated if the number of video lines per frame changes. Status is reported in the LINE_CNT_CHG bit in the RX_PORT_STS2 register.
4	IE_BUFFER_ERR	R/W	0x0	Interrupt on Receiver Buffer Error When enabled, an interrupt is generated if the Receive Buffer overflow is detected as reported in the BUFFER_ERROR bit in the RX_PORT_STS2 register.
3	RESERVED	R	0x0	Reserved
2	IE_V3LINK_PAR_ERR	R/W	0x0	Interrupt on V3Link Receiver Parity Error When enabled, an interrupt is generated on detection of parity errors on the V3Link interface for the receive port. Parity error status is reported in the PARITY_ERROR bit in the RX_PORT_STS1 register.
1	IE_PORT_PASS	R/W	0x0	Interrupt on change in Port PASS status When enabled, an interrupt is generated on a change in receiver port valid status as reported in the PORT_PASS bit in the PORT_STS1 register.
0	IE_LOCK_STS	R/W	0x0	Interrupt on change in Lock Status When enabled, an interrupt is generated on a change in lock status. Status is reported in the LOCK_STS_CHG bit in the PORT_STS1 register.

7.6.1.151 PORT_ISR_HI Register (Address = 0xDA) [Reset = 0x00]

PORT_ISR_HI is shown in Table 7-172.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-172 PORT_ISR_HI Register Field Descriptions

Bit	Field	Type	Reset	Description
7:3	RESERVED	R	0x0	Reserved
2	IS_V3LINK_ENC_ERR	R	0x0	V3Link Receiver Encode Error Interrupt Status An encoding error on the V3Link interface for the receive port has been detected. Status is reported in the V3LINK_ENC_ERROR bit in the RX_PORT_STS2 register. This interrupt condition is cleared by reading the RX_PORT_STS2 register.
1	IS_BCC_SEQ_ERR	R	0x0	BCC CRC Sequence Error Interrupt Status A Sequence Error has been detected for the Bi-directional Control Channel forward channel receiver. Status is reported in the BCC_SEQ_ERROR bit in the RX_PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register.
0	IS_BCC_CRC_ERR	R	0x0	BCC CRC error detect Interrupt Status A CRC error has been detected on a Bi-directional Control Channel frame received over the V3Link forward channel. Status is reported in the BCC_CRC_ERROR bit in the RX_PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register.

7.6.1.152 PORT_ISR_LO Register (Address = 0xDB) [Reset = 0x00]

PORT_ISR_LO is shown in Table 7-173.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-173 PORT_ISR_LO Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0x0	Reserved
6	IS_LINE_LEN_CHG	R	0x0	Video Line Length Interrupt Status A change in video line length has been detected. Status is reported in the LINE_LEN_CHG bit in the RX_PORT_STS2 register. This interrupt condition is cleared by reading the RX_PORT_STS2 register.
5	IS_LINE_CNT_CHG	R	0x0	Video Line Count Interrupt Status A change in number of video lines per frame has been detected. Status is reported in the LINE_CNT_CHG bit in the RX_PORT_STS2 register. This interrupt condition is cleared by reading the RX_PORT_STS2 register.
4	IS_BUFFER_ERR	R	0x0	Receiver Buffer Error Interrupt Status A Receive Buffer overflow has been detected as reported in the BUFFER_ERROR bit in the RX_PORT_STS2 register. This interrupt condition is cleared by reading the RX_PORT_STS2 register.
3	RESERVED	R	0x0	Reserved
2	IS_V3LINK_PAR_ERR	R	0x0	V3Link Receiver Parity Error Interrupt Status A parity error on the V3Link interface for the receive port has been detected. Parity error status is reported in the PARITY_ERROR bit in the RX_PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register.
1	IS_PORT_PASS	R	0x0	Port Valid Interrupt Status A change in receiver port valid status as reported in the PORT_PASS bit in the PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register.
0	IS_LOCK_STS	R	0x0	Lock Interrupt Status A change in lock status has been detected. Status is reported in the LOCK_STS_CHG bit in the RX_PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register.

7.6.1.153 FC_GPIO_STS Register (Address = 0xDC) [Reset = 0x00]

FC_GPIO_STS is shown in Table 7-174.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-174 FC_GPIO_STS Register Field Descriptions

Bit	Field	Type	Reset	Description
7	GPIO3_INT_STS	RC	0x0	GPIO3 Interrupt Status This bit indicates an interrupt condition has been met for GPIO3. This bit is cleared on read.
6	GPIO2_INT_STS	RC	0x0	GPIO2 Interrupt Status This bit indicates an interrupt condition has been met for GPIO2. This bit is cleared on read.
5	GPIO1_INT_STS	RC	0x0	GPIO1 Interrupt Status This bit indicates an interrupt condition has been met for GPIO1. This bit is cleared on read.
4	GPIO0_INT_STS	RC	0x0	GPIO0 Interrupt Status This bit indicates an interrupt condition has been met for GPIO0. This bit is cleared on read.
3	FC_GPIO3_STS	R	0x0	Forward Channel GPIO3 Status This bit indicates the current value for forward channel GPIO3.
2	FC_GPIO2_STS	R	0x0	Forward Channel GPIO2 Status This bit indicates the current value for forward channel GPIO2.
1	FC_GPIO1_STS	R	0x0	Forward Channel GPIO1 Status This bit indicates the current value for forward channel GPIO1.
0	FC_GPIO0_STS	R	0x0	Forward Channel GPIO0 Status This bit indicates the current value for forward channel GPIO0.

7.6.1.154 FC_GPIO_ICR Register (Address = 0xDD) [Reset = 0x00]

FC_GPIO_ICR is shown in Table 7-175.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-175 FC_GPIO_ICR Register Field Descriptions

Bit	Field	Type	Reset	Description
7	GPIO3_FALL_IE	W	0x0	GPIO3 Fall Interrupt Enable If this bit is set, an interrupt will be generated based on detection of a falling edge on GPIO3.
6	GPIO3_RISE_IE	W	0x0	GPIO3 Rise Interrupt Enable If this bit is set, an interrupt will be generated based on detection of a rising edge on GPIO3.
5	GPIO2_FALL_IE	W	0x0	GPIO2 Fall Interrupt Enable If this bit is set, an interrupt will be generated based on detection of a falling edge on GPIO2.
4	GPIO2_RISE_IE	W	0x0	GPIO2 Rise Interrupt Enable If this bit is set, an interrupt will be generated based on detection of a rising edge on GPIO2.
3	GPIO1_FALL_IE	W	0x0	GPIO1 Fall Interrupt Enable If this bit is set, an interrupt will be generated based on detection of a falling edge on GPIO1.
2	GPIO1_RISE_IE	W	0x0	GPIO1 Rise Interrupt Enable If this bit is set, an interrupt will be generated based on detection of a rising edge on GPIO1.
1	GPIO0_FALL_IE	W	0x0	GPIO0 Fall Interrupt Enable If this bit is set, an interrupt will be generated based on detection of a falling edge on GPIO0.
0	GPIO0_RISE_IE	W	0x0	GPIO0 Rise Interrupt Enable If this bit is set, an interrupt will be generated based on detection of a rising edge on GPIO0.

7.6.1.155 SEN_INT_RISE_STS Register (Address = 0xDE) [Reset = 0x00]

SEN_INT_RISE_STS is shown in Table 7-176.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-176 SEN_INT_RISE_STS Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	SEN_INT_RISE	RC	0x0	Sensor Interrupt Rise Status This register provides the interrupt status for rising edge transitions on the bits in SENSOR_STS_0. If a mask bit is set in the SEN_INT_RISE_MASK register, a rising edge transition on the corresponding SENSOR_STS_0 bit will generate an interrupt that will be latched in this register.

7.6.1.156 SEN_INT_FALL_STS Register (Address = 0xDF) [Reset = 0x00]

SEN_INT_FALL_STS is shown in Table 7-177.

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RX port-specific register. The V3Link Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.

Table 7-177 SEN_INT_FALL_STS Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	SEN_INT_FALL	RC	0x0	Sensor Interrupt Fall Status This register provides the interrupt status for falling edge transitions on the bits in SENSOR_STS_0. If a mask bit is set in the SEN_INT_FALL_MASK register, a falling edge transition on the corresponding SENSOR_STS_0 bit will generate an interrupt that will be latched in this register.

7.6.1.157 V3LINK_RX_ID0 Register (Address = 0xF0) [Reset = 0x5F]

V3LINK_RX_ID0 is shown in Table 7-178.

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Table 7-178 V3LINK_RX_ID0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	V3LINK_RX_ID0	R	0x5F	V3LINK_RX_ID0: First byte ID code: '_ '

7.6.1.158 V3LINK_RX_ID1 Register (Address = 0xF1) [Reset = 0x55]

V3LINK_RX_ID1 is shown in Table 7-179.

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Table 7-179 V3LINK_RX_ID1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	V3LINK_RX_ID1	R	0x55	V3LINK_RX_ID1: 2nd byte of ID code: 'U '

7.6.1.159 V3LINK_RX_ID2 Register (Address = 0xF2) [Reset = 0x42]

V3LINK_RX_ID2 is shown in Table 7-180.

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Table 7-180 V3LINK_RX_ID2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	V3LINK_RX_ID2	R	0x42	V3LINK_RX_ID2: 3rd byte of ID code: 'B '

7.6.1.160 V3LINK_RX_ID3 Register (Address = 0xF3) [Reset = 0x39]

V3LINK_RX_ID3 is shown in Table 7-181.

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Table 7-181 V3LINK_RX_ID3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	V3LINK_RX_ID3	R	0x39	V3LINK_RX_ID3: 4th byte of ID code: '9 '

7.6.1.161 V3LINK_RX_ID4 Register (Address = 0xF4) [Reset = 0x36]

V3LINK_RX_ID4 is shown in Table 7-182.

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Table 7-182 V3LINK_RX_ID4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	V3LINK_RX_ID4	R	0x36	V3LINK_RX_ID4: 5th byte of ID code: '6'

7.6.1.162 V3LINK_RX_ID5 Register (Address = 0xF5) [Reset = 0x30]

V3LINK_RX_ID5 is shown in Table 7-183.

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Table 7-183 V3LINK_RX_ID5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	V3LINK_RX_ID5	R	0x30	V3LINK_RX_ID5: 6th byte of ID code: '0'

7.6.1.163 I2C_RX0_ID Register (Address = 0xF8) [Reset = 0x00]

I2C_RX0_ID is shown in Table 7-184.

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As an alternative to paging to access V3Link receive port 0 registers, a separate I2C address may be enabled to allow direct access to the port 0 specific registers. The I2C_RX_0_ID register provides a simpler method of accessing device registers specifically for port 0 without having to use the paging function to select the register page. Using this address also allows access to all shared registers.

Table 7-184 I2C_RX0_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RX_PORT0_ID	R/W	0x0	7-bit Receive Port 0 I2C ID Configures the decoder for detecting transactions designated for Receiver port 0 registers. This provides a simpler method of accessing device registers specifically for port 0 without having to use the paging function to select the register page. A value of 0 in this field disables the Port0 decoder.
0	RESERVED	R	0x0	Reserved

7.6.1.164 I2C_RX1_ID Register (Address = 0xF9) [Reset = 0x00]

I2C_RX1_ID is shown in Table 7-185.

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As an alternative to paging to access V3Link receive port 1 registers, a separate I2C address may be enabled to allow direct access to the port 1 specific registers. The I2C_RX_1_ID register provides a simpler method of accessing device registers specifically for port 1 without having to use the paging function to select the register page. Using this address also allows access to all shared registers.

Table 7-185 I2C_RX1_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RX_PORT1_ID	R/W	0x0	7-bit Receive Port 1 I2C ID Configures the decoder for detecting transactions designated for Receiver port 1 registers. This provides a simpler method of accessing device registers specifically for port 1 without having to use the paging function to select the register page. A value of 0 in this field disables the Port1 decoder.
0	RESERVED	R	0x0	Reserved

7.6.1.165 I2C_RX2_ID Register (Address = 0xFA) [Reset = 0x00]

I2C_RX2_ID is shown in Table 7-186.

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As an alternative to paging to access V3Link receive port 2 registers, a separate I2C address may be enabled to allow direct access to the port 2 specific registers. The I2C_RX_2_ID register provides a simpler method of accessing device registers specifically for port 2 without having to use the paging function to select the register page. Using this address also allows access to all shared registers.

Table 7-186 I2C_RX2_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RX_PORT2_ID	R/W	0x0	7-bit Receive Port 2 I2C ID Configures the decoder for detecting transactions designated for Receiver port 2 registers. This provides a simpler method of accessing device registers specifically for port 2 without having to use the paging function to select the register page. A value of 0 in this field disables the Port2 decoder.
0	RESERVED	R	0x0	Reserved

7.6.1.166 I2C_RX3_ID Register (Address = 0xFB) [Reset = 0x00]

I2C_RX3_ID is shown in Table 7-187.

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As an alternative to paging to access V3Link receive port 3 registers, a separate I2C address may be enabled to allow direct access to the port 3 specific registers. The I2C_RX_3_ID register provides a simpler method of accessing device registers specifically for port 3 without having to use the paging function to select the register page. Using this address also allows access to all shared registers.

Table 7-187 I2C_RX3_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RX_PORT3_ID	R/W	0x0	7-bit Receive Port 3 I2C ID Configures the decoder for detecting transactions designated for Receiver port 3 registers. This provides a simpler method of accessing device registers specifically for port 3 without having to use the paging function to select the register page. A value of 0 in this field disables the Port3 decoder.
0	RESERVED	R	0x0	Reserved