SBOS932C January 2020 – March 2021 THP210
The sample-and-hold operating behavior of SAR ADCs causes charge transients at the input stage, and thus to the output stage of the amplifier. The RC filter helps to attenuate the sampling charge injection from the switched capacitor input stage of the ADC. A careful design is critical to meet linearity and noise performance of the ADC.
Choose the capacitor to be at least 10 times larger than the specified value of the SAR ADC sampling capacitor. A trade-off must be considered for the isolation resistor, where a higher damping effect is achieved at higher values, and lower value provide better THD at the input of the ADC. To select the best RC combination, use the Analog Engineering Tool.
One important element to consider is that the small-signal bandwidth of the FDA (fSSBW_FDA) determines what the cutoff frequency of the RC filter combination can be driven at the inputs of the ADC. Depending whether a single-ended filter or a differential filter is used the minimum required small-signal bandwidth of the FDA (fSSBW_FDA) can be estimated by Equation 4:
Driving higher capacitive loads degrades the phase margin of the FDA, and causes instability issues. Best practice is to perform a SPICE simulation using TINA-TI™ simulation software to confirm that the desired circuit is stable; that is, the FDA has more than a 45° phase margin.