SBOS932C January   2020  – March 2021 THP210

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Characterization Configuration
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Super-Beta Input Bipolar Transistors
      2. 8.3.2 Power Down
      3. 8.3.3 Flexible Gain Setting
      4. 8.3.4 Amplifier Overload Power Limit
      5. 8.3.5 Unity Gain Stability
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 I/O Headroom Considerations
      2. 9.1.2 DC Precision Analysis
        1. 9.1.2.1 DC Error Voltage at Room Temperature
        2. 9.1.2.2 DC Error Voltage Over Temperature
      3. 9.1.3 Noise Analysis
      4. 9.1.4 Mismatch of External Feedback Network
      5. 9.1.5 Operating the Power-Down Feature
      6. 9.1.6 Driving Capacitive Loads
      7. 9.1.7 Driving Differential ADCs
        1. 9.1.7.1 RC Filter Selection (Charge Kickback Filter)
        2. 9.1.7.2 Settling Time Driving the ADC Sample-and-Hold Operating Behavior
        3. 9.1.7.3 THD Performance
    2. 9.2 Typical Applications
      1. 9.2.1 MFB Filter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 ADS891x With Single-Ended RC Filter Stage
        1. 9.2.2.1 Design Requirements
          1. 9.2.2.1.1 Measurement Results
      3. 9.2.3 Attenuation Configuration Drives the ADS8912B
        1. 9.2.3.1 Design Requirements
          1. 9.2.3.1.1 Measurement Results
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout Recommendations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1.7.1 RC Filter Selection (Charge Kickback Filter)

The sample-and-hold operating behavior of SAR ADCs causes charge transients at the input stage, and thus to the output stage of the amplifier. The RC filter helps to attenuate the sampling charge injection from the switched capacitor input stage of the ADC. A careful design is critical to meet linearity and noise performance of the ADC.

Figure 9-8 and Figure 9-9 show a single-ended and differential filter approach, respectively.

GUID-808D5427-8AE3-4A63-9FD1-B2BCE89E5511-low.gifFigure 9-8 Single-Ended Filter
GUID-4F36D342-94C0-40D7-ACC9-4F2DEEECBF15-low.gifFigure 9-9 Differential Filter

Choose the capacitor to be at least 10 times larger than the specified value of the SAR ADC sampling capacitor. A trade-off must be considered for the isolation resistor, where a higher damping effect is achieved at higher values, and lower value provide better THD at the input of the ADC. To select the best RC combination, use the Analog Engineering Tool.

One important element to consider is that the small-signal bandwidth of the FDA (fSSBW_FDA) determines what the cutoff frequency of the RC filter combination can be driven at the inputs of the ADC. Depending whether a single-ended filter or a differential filter is used the minimum required small-signal bandwidth of the FDA (fSSBW_FDA) can be estimated by Equation 4:

Equation 4. GUID-D304109A-E815-42E6-92F9-3B672D917668-low.gif

where:

  • SEL = 1 for single-ended filter, SEL = 2 for differential filter

Driving higher capacitive loads degrades the phase margin of the FDA, and causes instability issues. Best practice is to perform a SPICE simulation using TINA-TI™ simulation software to confirm that the desired circuit is stable; that is, the FDA has more than a 45° phase margin.