SBOS932C January   2020  – March 2021 THP210

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Characterization Configuration
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Super-Beta Input Bipolar Transistors
      2. 8.3.2 Power Down
      3. 8.3.3 Flexible Gain Setting
      4. 8.3.4 Amplifier Overload Power Limit
      5. 8.3.5 Unity Gain Stability
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 I/O Headroom Considerations
      2. 9.1.2 DC Precision Analysis
        1. 9.1.2.1 DC Error Voltage at Room Temperature
        2. 9.1.2.2 DC Error Voltage Over Temperature
      3. 9.1.3 Noise Analysis
      4. 9.1.4 Mismatch of External Feedback Network
      5. 9.1.5 Operating the Power-Down Feature
      6. 9.1.6 Driving Capacitive Loads
      7. 9.1.7 Driving Differential ADCs
        1. 9.1.7.1 RC Filter Selection (Charge Kickback Filter)
        2. 9.1.7.2 Settling Time Driving the ADC Sample-and-Hold Operating Behavior
        3. 9.1.7.3 THD Performance
    2. 9.2 Typical Applications
      1. 9.2.1 MFB Filter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 ADS891x With Single-Ended RC Filter Stage
        1. 9.2.2.1 Design Requirements
          1. 9.2.2.1.1 Measurement Results
      3. 9.2.3 Attenuation Configuration Drives the ADS8912B
        1. 9.2.3.1 Design Requirements
          1. 9.2.3.1.1 Measurement Results
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout Recommendations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at TA = 25°C, VS (dual supply) = ±1.5 V to ±18 V, VVOCM = VICM = 0 V, RF = 2 kΩ, RL = 10 kΩ(1) , gain = –1 V/V, VPD = VVS+, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VIO Input-referred offset voltage 10 ±40 µV
TA = –40°C to +125°C ±75
Input offset voltage drift TA = –40°C to +125°C 0.1 ±0.35 µV/°C
PSRR Power-supply rejection ratio ±0.025 ±0.25 µV/V
TA = –40°C to +125°C ±0.5
INPUT BIAS CURRENT
IB Input bias current ±0.2 ±2 nA
TA = –40°C to +125°C ±4
Input bias current drift TA = –40°C to  +125°C ±2 ±15 pA/°C
IOS Input offset current ±0.2 ±1 nA
TA = –40°C to +125°C ±3
Input offset current drift TA = –40°C to +125°C 1 ±10 pA/°C
NOISE
en Input differential voltage noise f = 1 kHz 3.7 nV/√Hz
f = 10 Hz 4
f = 0.1 to 10 Hz 0.1 µVPP
ei Input current noise, each input f = 1 kHz 300 fA/√Hz
f = 10 Hz 400
f = 0.1 to 10 Hz 13.4 pAPP
INPUT VOLTAGE
Common-mode voltage range TA = –40°C to +125°C VVS– + 1 VVS+ – 1 V
CMRR Common-mode rejection ratio VVS– + 1 V ≤ VICM ≤ VVS+ – 1 V
140

 dB
VVS– + 1 V ≤ VICM ≤ VVS+ – 1 V, VS = ±18 V 126 140
VVS– + 1 V ≤ VICM ≤ VVS+ – 1 V, VS = ±18 V, TA = –40°C to   +125°C 120
INPUT IMPEDANCE
Input impedance differential mode VICM = 0 V 1 || 1 GΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = ±2.5 V, VVS– + 0.2 V < VO < VVS+ – 0.2 V 115 120 dB
VS = ±2.5 V, VVS– + 0.3 V < VO < VVS+ – 0.3 V, TA = –40°C to +125°C 110 120
VS = ±15 V, VVS– + 0.6 V < VO < VVS+ – 0.6 V 115 120
VS = ±15 V, VVS– + 0.6 V < VO < VVS+ – 0.6 V,
TA = –40°C to +125°C		 110 120
FREQUENCY RESPONSE
SSBW Small-signal bandwidth VO = 100 mVPP 7 MHz
GBP Gain-bandwidth product VO = 100 mVPP, gain = –10 V/V 9.2 MHz
FBP Full-power bandwidth VO = 1 VPP 2.4 MHz
SR Slew rate 10-V step 15 V/µs
Settling time To 0.1% of final value, VO = 10-V step 1 µs
To 0.01% of final value, VO= 10-V step 1.2
THD+N Total harmonic distortion and noise Differential input, f = 1 kHz, VO = 10 VPP –120 dB
THD+N Total harmonic distortion and noise Single-ended input, f = 1 kHz, VO = 10 VPP –115
THD+N Total harmonic distortion and noise Differential input, f = 10 kHz, VO = 10 VPP –112
Total harmonic distortion and noise Single-ended input, f = 10 kHz, VO = 10 VPP –107
HD2 Second-order harmonic distortion Differential input, f = 1 kHz, VO = 10 VPP –120
Single-ended input, f = 1 kHz, VO = 10 VPP –126
HD3 Third-order harmonic distortion Differential input, f = 1 kHz, VO = 10 VPP –120
Single-ended input, f = 1 kHz, VO = 10 VPP –119
Overdrive recovery time gain = –5 V/V, 2x output overdrive, dc-coupled 3.3 µs
ZO Open-loop output impedance f = 100 kHz (differential) 14 Ω
CLOAD Capacitive load drive Differential capacitive load, no output isolation resistors, phase margin = 30° 50 pF
OUTPUT
VOL Negative output voltage swing from rail VS = ±2.5 V 100 mV
VS = ±2.5 V, TA = –40°C to +125°C 100
VS = ±18 V 230
VS = ±18 V, TA = –40°C to +125°C 270
VOH Positive output voltage swing from rail VS = ±2.5 V 100
VS = ±2.5 V, TA = –40°C to +125°C 100
VS = ±18 V 230
VS = ±18 V, TA = –40°C to +125°C 270
ISC Short-circuit current ±31 mA
OUTPUT COMMON-MODE VOLTAGE
Small-signal bandwidth from VOCM pin VVOCM = 100 mVPP 2 MHz
Large-signal bandwidth from VOCM pin VVOCM = 0.6 VPP 5.7
Slew rate from VOCM pin VVOCM = 0.5-V step, rising 4.2 V/µs
VVOCM = 0.5-V step, falling 5.5
DC output balance VVOCM fixed midsupply (VO = ±1 V) 78 dB
VOCM Input voltage range VS = ±2.5 V VVS– + 1 VVS+ – 1 V
VS = ±18 V VVS– + 2 VVS+ – 2
VOCM input impedance 2.5  || 1 MΩ || pF
VOCM offset from mid-supply VVOCM pin floating, VO = VICM = 0 V ±1 mV
VOCM common-mode offset voltage VVOCM = VICM, VO = 0 V ±1 ±6
VVOCM = VICM, VO = 0 V, TA = –40°C to +125°C ±10
VOCM common-mode offset voltage drift VVOCM = VICM, VO = 0 V, TA = –40°C to +125°C ±20 ±60 µV/°C
POWER SUPPLY
IQ Quiescent operating current 0.95 1.05 mA
TA = –40°C to +125°C 1.4
POWER DOWN
V PD(HI) Power-down enable voltage TA = –40°C to +125°C VVS+ – 0.5 V
V PD(LOW) Power-down disable voltage TA = –40°C to +125°C VVS+ – 2.0
PD bias current V PD  = VVS+ – 2 V 1 2 µA
Powerdown quiescent current 10 20 µA
Turn-on time delay VIN = 100 mV, Time to VO = 90% of final value 10 µs
Turn-off time delay VIN = 100 mV, Time to VO = 10% of original value 15
(1) RL is connected differentially, from OUT+ to OUT–.