SBOS874D August   2017  – February 2021 THS4561

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS+ – VS– = 5 V to 12 V
    6. 7.6 Typical Characteristics: (VS+) – (VS–) = 12 V
    7. 7.7 Typical Characteristics: (VS+) – (VS–) = 5 V
    8. 7.8 Typical Characteristics: (VS+) – (VS–) = 3 V
    9. 7.9 Typical Characteristics: (VS+) – (VS–) = 3-V to 12-V Supply Range
  8. Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
    2. 8.2 Output Interface Circuit for DC-Coupled Differential Testing
    3. 8.3 Output Common-Mode Measurements
    4. 8.4 Differential Amplifier Noise Measurements
    5. 8.5 Balanced Split-Supply Versus Single-Supply Characterization
    6. 8.6 Simulated Characterization Curves
    7. 8.7 Terminology and Application Assumptions
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Down Mode
      2. 9.4.2 Single-Ended Source to Differential Output Mode
        1. 9.4.2.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions
        2. 9.4.2.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions
      3. 9.4.3 Differential Input to a Differential Output Mode
        1. 9.4.3.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Differential Open-Loop Gain and Output Impedance
      2. 10.1.2 Setting Resistor Values Versus Gain
      3. 10.1.3 Noise Analysis
      4. 10.1.4 Factors Influencing Harmonic Distortion
      5. 10.1.5 Input Overdrive Performance
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Layout Recommendations
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Board Layout Recommendations

Similar to all high-speed devices, best system performance is achieved with close attention to board layout. The provides a good example of high-frequency layout techniques as a reference. This EVM includes numerous extra elements and features for characterization purposes that may not apply to some applications. General high-speed signal path layout suggestions include:

  • Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs; however, both ground and power planes must be opened up around the capacitive sensitive input and output device pins. When the signal goes to a resistor, parasitic capacitance becomes more of a band-limiting issue and less of a stability issue.
  • Good high-frequency decoupling capacitors (0.1 µF) are required to a ground plane at the device power pins. Additional higher-value capacitors (2.2 µF) are also required but can be placed further from the device power pins and shared among devices. For best high-frequency decoupling, consider X2Y supply decoupling capacitors that offer a much higher self-resonance frequency over standard capacitors.
  • Differential signal routing over any appreciable distance must use microstrip layout techniques with matched impedance traces.
  • The input summing junctions are very sensitive to parasitic capacitance. Any RG elements must connect into the summing junction with minimal trace length to the device pin side of the resistor. The other side of the RG elements can have more trace length if needed to the source or to GND.