SLOS154C December   1995  – July 2025 TLC27L1 , TLC27L1A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Dissipation Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Electrical Characteristics, C Suffix
    5. 5.5  Operating Characteristics, VDD = 5V, C Suffix
    6. 5.6  Operating Characteristics, VDD = 10V, C Suffix
    7. 5.7  Electrical Characteristics, I Suffix
    8. 5.8  Operating Characteristics, VDD = 5V, I Suffix
    9. 5.9  Operating Characteristics, VDD = 10V, I Suffix
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Single-Supply Versus Split-Supply Test Circuits
    2. 6.2 Input Bias Current
    3. 6.3 Low-Level Output Voltage
    4. 6.4 Input Offset Voltage Temperature Coefficient
    5. 6.5 Full-Power Response
    6. 6.6 Test Time
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Single-Supply Operation
      2. 7.1.2 Input Characteristics
      3. 7.1.3 Noise Performance
      4. 7.1.4 Feedback
      5. 7.1.5 Electrostatic Discharge Protection
      6. 7.1.6 Latch-Up
      7. 7.1.7 Output Characteristics
      8. 7.1.8 Typical Applications
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Revision History

Changes from Revision B (June 2005) to Revision C (July 2025)

  • Deleted obsolete TLC27L1AI, TLC27L1BI, TLC27L1BC, and TLC27L1M devices and associated content from documentGo
  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Added Applications, Pin Configuration and Functions, Application and Implementation, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sectionsGo
  • Added Applications sectionGo
  • Deleted Equivalent Schematic sectionGo
  • Added Pin Configuration and Functions section with pin descriptionsGo
  • Added table note that input bias current and input offset current are specified by characterizationGo
  • Changed typical input offset current from 0.1pA to 0.5pAGo
  • Changed typical minimum input common-mode voltage for TA = 25°C from −0.3V to −0.2VGo
  • Changed typical low-level output voltage from 0mV to 1mV for VDD = 5V, and from 0mV to 5mV for VDD = 10VGo
  • Changed typical CMRR for VDD = 5V at TA = 25°C from 94dB to 87dBGo
  • Changed typical CMRR for VDD = 5V at TA = 70°C and TA = 0°C from 95dB to 85dBGo
  • Changed typical CMRR for VDD = 10V at TA = 25°C from 97dB to 94dBGo
  • Changed typical CMRR for VDD =10V at TA = 0°C and TA = 70°C from 97dB to 93dBGo
  • Changed parameter name from Input current (BIAS SELECT) to Offset adjustment pin input current (BIAS SELECT), and added "legacy silicon" to test conditions Go
  • Changed typical unity-gain bandwidth at TA = 0°C from 125kHz to 110kHz in Operating Characteristics for VDD = 10V, C Suffix Go
  • Added table note that input bias current and input offset current are specified by characterizationGo
  • Changed typical input offset current from 0.1pA to 0.5pAGo
  • Changed typical minimum input common-mode voltage for TA = 25°C from −0.3V to −0.2VGo
  • Changed typical low-level output voltage from 0mV to 1mV for VDD = 5V, and from 0mV to 5mV for VDD = 10VGo
  • Changed typical CMRR for VDD = 5V at TA = 25°C from 94dB to 87dBGo
  • Changed typical CMRR for VDD = 5V at TA = 85°C and TA = −40°C from 95dB to 85dBGo
  • Changed typical CMRR for VDD = 10V at TA = 25°C from 97dB to 94dBGo
  • Changed typical CMRR for VDD =10V at TA = 85°C from 97dB to 93dBGo
  • Changed typical CMRR for VDD = 10V at TA = −40°C from 98dB to 93dBGo
  • Changed parameter name from Input current (BIAS SELECT) to Offset adjustment pin input current (BIAS SELECT), and added "legacy silicon" to test conditionsGo
  • Changed typical unity-gain bandwidth at TA = −40°C from 130kHz to 110kHz in Operating Characteristics for VDD = 5V, I Suffix Go
  • Changed typical unity-gain bandwidth at TA = −40°C from 155kHz to 110kHz in Operating Characteristics for VDD = 10V, I Suffix Go
  • Deleted Figures 25 and 26Go
  • Updated Figure 5-30Go
  • Updated description of full-linear and full-peak responses in Full-Power Response Go
  • Deleted Input Offset Voltage Nulling sectionGo
  • Added guidance concerning removal of bias-select pin function and changes to input crossover region to Input Characteristics Go
  • Deleted Figure 47 in Output Characteristics Go
  • Updated Figures 7-12 and 7-13 in Output Characteristics to correct amplifier feedback connectionsGo