SBAS906 March 2018 TLV320ADC3100
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Source of Primary BCLK | Source of Secondary BCLK | Source of Primary WCLK | Source of Secondary WCLK | Reserved | Reserved | ||
R/W-0h | R/W-0h | R/W-01h | R/W-00h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | Source of Primary BCLK | R/W | 0h | 0: Primary BCLK output = internally generated BCLK clock
1: Primary BCLK output = secondary BCLK |
6 | Source of Secondary BCLK | R/W | 0h | 0: Secondary BCLK output = primary BCLK
1: Secondary BCLK output = internally generated BCLK clock |
5:4 | Source of Primary WCLK | R/W | 01h | 00: Reserved. Do not use.
01: Primary WCLK output = internally generated ADC_fS clock (default) 10: Primary WCLK output = secondary WCLK 11: Reserved. Do not use. |
3:2 | Source of Secondary WCLK | R/W | 00h | 00: Secondary WCLK output = primary WCLK
01: Reserved. Do not use. 10: Secondary WCLK output = internally generated ADC_fS clock 11: Reserved. Do not use. |
1:0 | Reserved | R | 0h | Reserved. Do not write any value other than reset value. |