SBOS966H april   2019  – june 2023 TLV9061-Q1 , TLV9062-Q1 , TLV9064-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information: TLV9061-Q1
    5. 8.5 Thermal Information: TLV9062-Q1
    6. 8.6 Thermal Information: TLV9064-Q1
    7. 8.7 Electrical Characteristics
    8. 8.8 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Rail-to-Rail Input
      2. 9.3.2 Rail-to-Rail Output
      3. 9.3.3 Overload Recovery
      4. 9.3.4 Shutdown Function
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Typical Low-Side Current Sense Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Typical Comparator Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Input and ESD Protection
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.7 Electrical Characteristics

For VS (total supply voltage) = (V+) – (V–) = 1.8 V to 5.5 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
OFFSET VOLTAGE
VOSInput offset voltageVS = 5 V±0.3±1.85mV
VS = 5 V, TA = –40°C to 125°C±2
dVOS/dTDriftVS = 5 V, TA = –40°C to 125°C±0.53µV/°C
PSRRPower-supply rejection ratioVS = 1.8 V – 5.5 V, VCM = (V–)±7±80µV/V
Channel separation, DCAt DC100dB
INPUT VOLTAGE RANGE
VCMCommon-mode voltage rangeVS = 1.8 V to 5.5 V(V–) – 0.1(V+) + 0.1V
CMRRCommon-mode rejection ratioVS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C		80103dB
VS = 5.5 V, VCM = –0.1 V to 5.6 V
TA = –40°C to 125°C		5775
VS = 1.8 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
TA = –40°C to 125°C		88
VS = 1.8 V, VCM = –0.1 V to 1.9 V
TA = –40°C to 125°C		70
INPUT BIAS CURRENT
IBInput bias current±5pA
IOSInput offset current±5pA
NOISE
EnInput voltage noise (peak-to-peak)VS = 5 V, f = 0.1 Hz to 10 Hz4.77µVPP
enInput voltage noise densityVS = 5 V, f = 10 kHz10nV/√ Hz
VS = 5 V, f = 1 kHz16
inInput current noise densityf = 1 kHz23fA/√ Hz
INPUT CAPACITANCE
CIDDifferential2pF
CICCommon-mode4pF
OPEN-LOOP GAIN
AOLOpen-loop voltage gainVS = 1.8 V, (V–) + 0.04 V < VO < (V+) – 0.04 V,
RL = 10 kΩ		100dB
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ		104130
VS = 1.8 V, (V–) + 0.06 V < VO < (V+) – 0.06 V,
RL = 2 kΩ		100
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ		130
FREQUENCY RESPONSE
GBPGain bandwidth productVS = 5 V, G = +110MHz
φmPhase marginVS = 5 V, G = +155°
SRSlew rateVS = 5 V, G = +16.5V/µs
tSSettling timeTo 0.1%, VS = 5 V, 2-V step , G = +1, CL = 100 pF0.5µs
To 0.01%, VS = 5 V, 2-V step,
G = +1, CL = 100 pF		1
tOROverload recovery timeVS = 5 V, VIN  × gain > VS0.2µs
THD + NTotal harmonic distortion + noise(1)VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1,
f = 1 kHz		0.0008%
OUTPUT
VOVoltage output swing from supply railsVS = 5.5 V, RL = 10 kΩ20mV
VS = 5.5 V, RL = 2 kΩ60
ISCShort-circuit currentVS = 5 V±50mA
ZOOpen-loop output impedanceVS = 5 V, f = 10 MHz100Ω
POWER SUPPLY
IQQuiescent current per amplifierVS = 5.5 V, IO = 0 mA538750µA
VS = 5.5 V, IO = 0 mA TA = –40°C to 125°C800
SHUTDOWN (2)
IQSDQuiescent current per amplifierVS = 1.8 V to 5.5 V, all amplifiers disabled, SHDN = Low0.51.5µA
ZSHDNOutput impedance during shutdownVS = 1.8 V to 5.5 V, amplifier disabled10 || 8GΩ || pF
VSHDN_THR_HIHigh level voltage shutdown threshold (amplifier enabled)VS = 1.8 V to 5.5 V(V–) + 0.9(V–) + 1.1V
VSDHN_THR_LOLow level voltage shutdown threshold (amplifier disabled)VS = 1.8 V to 5.5 V(V–) + 0.2(V–) + 0.7V
tONAmplifier enable time (shutdown)(3)VS = 1.8 V to 5.5 V, full shutdown; G = 1, VOUT = 0.9 × VS / 2, RL connected to V–10µs
tOFFAmplifier disable time(3)VS = 1.8 V to 5.5 V, G = 1, VOUT = 0.1 × VS / 2, RL connected to V–0.6µs
SHDN pin input bias current (per pin)VS = 1.8 V to 5.5 V, V+ ≥ SHDN ≥ (V+) – 0.8 V130pA
VS = 1.8 V to 5.5 V, V– ≤ SHDN ≤ V– + 0.8 V40
(1) Third-order filter; bandwidth = 80 kHz at –3 dB.
(2) Ensured by design and characterization; not production tested.
(3) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.