SNIS217C december   2020  – may 2023 TMP139

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power-Up Sequence
      2. 7.3.2 Power-Down and Device Reset
      3. 7.3.3 Temperature Result and Limits
      4. 7.3.4 Bus Reset
      5. 7.3.5 Interrupt Generation
      6. 7.3.6 Parity Error Check
      7. 7.3.7 Packet Error Check
    4. 7.4 Device Functional Modes
      1. 7.4.1 Conversion Mode
      2. 7.4.2 Serial Address
      3. 7.4.3 I2C Mode Operation
        1. 7.4.3.1 Host I2C Write Operation
        2. 7.4.3.2 Host I2C Read Operation
        3. 7.4.3.3 Host I2C Read Operation in Default Read Address Pointer Mode
        4. 7.4.3.4 Switching from I2C Mode to I3C Basic Mode
      4. 7.4.4 I3C Basic Mode Operation
        1. 7.4.4.1 Host I3C Write Operation without PEC
        2. 7.4.4.2 Host I3C Write Operation with PEC
        3. 7.4.4.3 Host I3C Read Operation without PEC
        4. 7.4.4.4 Host I3C Read Operation with PEC
        5. 7.4.4.5 Host I3C Read Operation in Default Read Address Pointer Mode
      5. 7.4.5 In Band Interrupt
        1. 7.4.5.1 In Band Interrupt Arbitration Rules
        2. 7.4.5.2 In Band Interrupt Bus Transaction
      6. 7.4.6 Common Command Codes Support
        1. 7.4.6.1 ENEC CCC
        2. 7.4.6.2 DISEC CCC
        3. 7.4.6.3 RSTDAA CCC
        4. 7.4.6.4 SETAASA CCC
        5. 7.4.6.5 GETSTATUS CCC
        6. 7.4.6.6 DEVCAP CCC
        7. 7.4.6.7 SETHID CCC
        8. 7.4.6.8 DEVCTRL CCC
      7. 7.4.7 I/O Operation
      8. 7.4.8 Timing Diagrams
    5. 7.5 Programming
      1. 7.5.1 Enabling Interrupt Mechanism
      2. 7.5.2 Clearing Interrupt
    6. 7.6 Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YAH|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Timing Requirements

minimum and maximum specifications are over –40°C to 125°C and VDDIO = 0.95 V to 1.05 V (unless otherwise noted)(1)
I2C MODE - OPEN DRAIN I3C MODE - PUSH PULL(1) UNIT
MIN MAX MIN MAX
fSCL SCL operating frequency 0.01 1 0.001 12.5 MHz
tHiGH Clock pulse width high time (Figure 6-1) 260 35 ns
tLOW Clock pulse width low time (Figure 6-1) 500 35 ns
tTIMEOUT Detect clock low timeout (Figure 7-4) 10 50 10 50 ms
tR SDA rise time (Figure 6-1) 120 5 ns
tF SDA fall time (Figure 6-1) 4 120 5 ns
tSUDAT Data setup time (Figure 6-1) 50 8 ns
tHDDI Data hold timehref (Figure 6-1) 0 3 ns
tSUSTA START condition setup time (Figure 6-1) 260 12 ns
tHDSTA Hold time after repeated START condition. After this period, the first clock is generated. (Figure 6-1) 260 30 ns
tSUSTO STOP condition setup time (Figure 6-1) 260 12 ns
tBUF Time between STOP condition and next START condition (Figure 6-1) 500 500 ns
tAVAL Bus available time (no edges seen in SDA and SCL) 1 µs
tIBI_ISSUE Time to issue IBI after an event is detected when bus is available 15 µs
tCLR_I3C_CMD_DELAY Time from Clear Register Status to any I3C operation with START condition. PEC disabled 4 µs
Time from Clear Register Status to any I3C operation with START condition. PEC enabled 15 µs
tHDDAT SCL falling clock in to SDA data out hold time (Figure 6-4) 0.5 350 ns
tDOUT SCL falling clock in to SDA valid data out time (Figure 6-2, Figure 6-3, Figure 6-5) 0.5 12 ns
tDOFFS SCL rising clock in to SDA output off (Figure 6-2, Figure 6-3) 0.5 12 ns
tDOFFM SCL rising clock in to host controller SDA output off 0.5 30 ns
tCL_R_DAT_F SCL rising clock in to host controller driving SDA low (Figure 6-2) 40 ns
tDEVCTRLCCC_PEC_DIS DEVCTRL CCC followed by DEVCTRL CCC or register read/write command delay 3 3 µs
tWR_RD_DECLAY_PEC_EN Register write command followed by register read command delay in PEC enabled mode 8 µs
tI2C_CCC_UPDATE_DELAY SETHID CCC or SETAASA CCC to any other CCC or read/write command delay 2.5 µs
tI3C_CCC_UPDATE_DELAY RSTDAA CCC or ENEC CCC or DISEC CCC to any other CCC or read/write command delay 2.5 µs
tCCC_DELAY Any CCC to RSTDAA CCC delay 2.5 µs
(1) The host and device have the same VDD value. Values are based on statistical analysis of samples tested during initial release.
(2) The maximum t(HDDAT) can be 0.9 µs for fast mode, and is less than the maximum t(VDAT) by a transition time.