SPRSP45B March 2020 – December 2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1
PRODUCTION DATA
The following section contains the SPI Master Mode Timings. For more information about the SPI in High-Speed mode, see the Serial Peripheral Interface (SPI) chapter of the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual.
Section 7.14.5.1.1 lists the SPI master mode timing requirements.
Section 7.14.5.1.2 lists the SPI master mode switching characteristics where the clock phase = 0. Figure 7-58 shows the SPI master mode external timing where the clock phase = 0.
Section 7.14.5.1.3 lists the SPI master mode switching characteristics where the clock phase = 1. Figure 7-59 shows the SPI master mode external timing where the clock phase = 1.
All timing parameters for SPI High-Speed Mode assume a load capacitance of 5 pF on SPICLK, SPISIMO, and SPISOMI.