SCDS445B May   2022  – March 2023 TMUX4051 , TMUX4052 , TMUX4053

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Thermal Information: TMUX405x
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Electrical Characteristics
    6. 7.6 AC Performance Characteristics
    7. 7.7 Timing Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1  On-Resistance
    2. 8.2  Off-Leakage Current
    3. 8.3  On-Leakage Current
    4. 8.4  Transition Time
    5. 8.5  Break-Before-Make
    6. 8.6  tON(EN) and tOFF(EN)
    7. 8.7  Propagation Delay
    8. 8.8  Charge Injection
    9. 8.9  Off Isolation
    10. 8.10 Crosstalk
    11. 8.11 Bandwidth
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Bidirectional Operation
      2. 9.3.2 Rail-to-Rail Operation
      3. 9.3.3 1.8 V Logic Compatible Inputs
      4. 9.3.4 Device Functional Modes
      5. 9.3.5 Truth Tables
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
    3. 10.3 Design Requirements
    4. 10.4 Detailed Design Procedure
    5. 10.5 Application Curves
    6. 10.6 Power Supply Recommendations
    7. 10.7 Layout
      1. 10.7.1 Layout Guidelines
      2. 10.7.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

Figure 6-1 TMUX4051 PW Package,16-Pin TSSOP(Top View)
Figure 6-2 TMUX4051 DYY Package,16-Pin SOT-23-THIN(Top View)
Figure 6-3 TMUX4051 BQB Package,16-Pin WQFN(Top View)
Table 6-1 Pin Functions TMUX4051
PINTYPE#GUID-732ED030-F3CF-4441-8E65-168659731AC1/X5455DESCRIPTION#GUID-732ED030-F3CF-4441-8E65-168659731AC1/X5457
NAMENO.
S41I/OSource pin 4. Signal path can be an input or output.
S62I/OSource pin 6. Signal path can be an input or output.
D3I/ODrain pin (common). Signal path can be an input or output.
S74I/OSource pin 7. Signal path can be an input or output.
S55I/OSource pin 5. Signal path can be an input or output.
EN6IActive low logic enable. When this pin is high, all switches are turned off. Table 9-1 lists how the A[2:0] address inputs determine which switch is turned on when this pin is low.
VSS7PNegative power supply. This pin is the most negative power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
GND8PGround (0 V) reference
A29IAddress line 2. Table 9-1 provides information about how A2 controls the switch configuration.
A110IAddress line 1. Table 9-1 provides information about how A1 controls the switch configuration.
A011IAddress line 0. Table 9-1 provides information about how A0 controls the switch configuration.
S312I/OSource pin 3. Signal path can be an input or output.
S013I/OSource pin 0. Signal path can be an input or output.
S114I/OSource pin 1. Signal path can be an input or output.
S215I/OSource pin 2. Signal path can be an input or output.
VDD16PPositive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
Thermal pad—The thermal pad is not connected internally. It is recommended that the pad be left floating or tied to GND.
(1) I = input, O = output, I/O = input and output, P = power.
Figure 6-4 TMUX4052 PW Package,16-Pin TSSOP(Top View)
Figure 6-5 TMUX4052 DYY Package,16-Pin SOT-23-THIN(Top View)
Figure 6-6 TMUX4052 BQB Package,16-Pin WQFN(Top View)
Table 6-2 Pin Functions TMUX4052
PINTYPE#GUID-732ED030-F3CF-4441-8E65-168659731AC1/X5456DESCRIPTION#GUID-732ED030-F3CF-4441-8E65-168659731AC1/X5458
NAMENO.
S0B1I/OSource pin 0 of mux B. Can be an input or output.
S2B2I/OSource pin 2 of mux B. Can be an input or output.
DB3I/ODrain pin (common) of mux B. Can be an input or output.
S3B4I/OSource pin 3 of mux B. Can be an input or output.
S1B5I/OSource pin 1 of mux B. Can be an input or output.
EN6IActive low logic enable. When this pin is high, all switches are turned off. When this pin is low, the A[1:0] address inputs determine which switch is turned on.
VSS7PNegative power supply. This pin is the most negative power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
GND8PGround (0 V) reference
A19IAddress line 1. Table 9-2 provides information about how A1 controls the switch configuration.
A010IAddress line 0. Table 9-2 provides information about how A0 controls the switch configuration.
S3A11I/OSource pin 3 of mux A. Can be an input or output.
S0A12I/OSource pin 0 of mux A. Can be an input or output.
DA13I/ODrain pin (common) of mux A. Can be an input or output.
S1A14I/OSource pin 1 of mux A. Can be an input or output.
S2A15I/OSource pin 2 of mux A. Can be an input or output.
VDD16PPositive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
Thermal pad—The thermal pad is not connected internally. It is recommended that the pad be left floating or tied to GND.
(1) I = input, O = output, I/O = input and output, P = power.
Figure 6-7 TMUX4053 PW Package,16-Pin TSSOP(Top View)
Figure 6-8 TMUX4053 DYY Package,16-Pin SOT-23-THIN(Top View)
Figure 6-9 TMUX4053 BQB Package,16-Pin WQFN(Top View)
Table 6-3 Pin Functions TMUX4053
PINTYPE#GUID-732ED030-F3CF-4441-8E65-168659731AC1/X4557DESCRIPTION#GUID-732ED030-F3CF-4441-8E65-168659731AC1/X4567
NAMENO.
S2B1I/OSource pin B of switch 2. Can be an input or output.
S2A2I/OSource pin A of switch 2. Can be an input or output.
S3B3I/OSource pin B of switch 3. Can be an input or output.
D34I/ODrain pin (common) of switch 3. Can be an input or output.
S3A5I/OSource pin A of switch 3. Can be an input or output.
EN6IActive low logic enable. When this pin is high, all switches are turned off. When this pin is low, the SEL[x] logic control inputs determine which switch is turned on.
VSS7PNegative power supply. This pin is the most negative power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
GND8PGround (0 V) reference
SEL39ILogic control select pin 3. Table 9-3 provides controls switch 3 configuration.
SEL210ILogic control select pin 2. Table 9-3 provides controls switch 2 configuration.
SEL111ILogic control select pin 1. Table 9-3 provides controls switch 1 configuration.
S1A12I/OSource pin A of switch 1. Can be an input or output.
S1B13I/OSource pin B of switch 1. Can be an input or output.
D114I/ODrain pin (common) of switch 1. Can be an input or output.
D215I/ODrain pin (common) of switch 2. Can be an input or output.
VDD16PPositive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
Thermal pad—The thermal pad is not connected internally. It is recommended that the pad be left floating or tied to GND.
(1) I = input, O = output, I/O = input and output, P = power.