SCDS435 September   2021 TMUX8108 , TMUX8109

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings: TMUX810x Devices
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information: TMUX810x
    4. 6.4  Recommended Operating Conditions: TMUX810x Devices
    5. 6.5  Electrical Characteristics (Global): TMUX810x Devices
    6. 6.6  Electrical Characteristics (±36-V Dual Supply)
    7. 6.7  Electrical Characteristics (72-V Single Supply)
    8. 6.8  Electrical Characteristics (100-V Single Supply)
    9. 6.9  Switching Characteristics: TMUX810x Devices
    10. 6.10 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1  Truth Tables
    2. 7.2  On-Resistance
    3. 7.3  Off-Leakage Current
    4. 7.4  On-Leakage Current
    5. 7.5  Break-Before-Make Delay
    6. 7.6  Enable Delay Time
      1. 7.6.1 Device Turn On Time
    7. 7.7  Transition Time
    8. 7.8  Charge Injection
    9. 7.9  Off Isolation
    10. 7.10 Crosstalk
    11. 7.11 Bandwidth
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Flat On - Resistance
      2. 8.3.2 Protection Features
        1. 8.3.2.1 Fail-Safe Logic
        2. 8.3.2.2 Latch-up Immunity
      3. 8.3.3 Bidirectional Operation
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Latch-up Immunity

Latch-Up is a condition where a low impedance path is created between a supply pin and ground. This condition is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic damage due to excessive current levels. The Latch-Up condition typically requires a power cycle to eliminate the low impedance path.

In the TMUX8108 and TMUX8109 devices, an insulating oxide layer is placed on top of the silicon substrate to prevent any parasitic junctions from forming. As a result, the devices are latch-up immune under all circumstances by device construction.