SLASEN3B January   2018  – August 2018 TPA3220

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Audio Characteristics (BTL)
    7. 7.7 Audio Characteristics (PBTL)
    8. 7.8 Typical Characteristics, BTL Configuration, AD-mode
    9. 7.9 Typical Characteristics, PBTL Configuration, AD-mode
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Internal LDO
        1. 9.3.1.1 Input Configuration, Gain Setting And Master / Slave Operation
      2. 9.3.2 Gain Setting And Master / Slave Operation
      3. 9.3.3 AD-Mode and HEAD-Mode PWM Modulation
      4. 9.3.4 Oscillator
      5. 9.3.5 Input Impedance
      6. 9.3.6 Error Reporting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Powering Up
        1. 9.4.1.1 Startup Ramp Time
      2. 9.4.2 Powering Down
        1. 9.4.2.1 Power Down Ramp Time
      3. 9.4.3 Device Reset
      4. 9.4.4 Device Soft Mute
      5. 9.4.5 Device Protection System
        1. 9.4.5.1 Overload and Short Circuit Current Protection
        2. 9.4.5.2 Signal Clipping and Pulse Injector
        3. 9.4.5.3 DC Speaker Protection
        4. 9.4.5.4 Pin-to-Pin Short Circuit Protection (PPSC)
        5. 9.4.5.5 Overtemperature Protection OTW and OTE
        6. 9.4.5.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
        7. 9.4.5.7 Fault Handling
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo BTL Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedures
          1. 10.2.1.2.1 Decoupling Capacitor Recommendations
          2. 10.2.1.2.2 PVDD Capacitor Recommendation
          3. 10.2.1.2.3 BST capacitors
          4. 10.2.1.2.4 PCB Material Recommendation
      2. 10.2.2 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled before LC filter)
        1. 10.2.2.1 Design Requirements
      3. 10.2.3 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled after LC filter)
        1. 10.2.3.1 Design Requirements
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
      1. 11.1.1 VDD Supply
      2. 11.1.2 AVDD and GVDD Supplies
      3. 11.1.3 PVDD Supply
      4. 11.1.4 BST Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
      1. 12.2.1 BTL Application Printed Circuit Board Layout Example
      2. 12.2.2 PBTL (Outputs Paralleled before LC filter) Application Printed Circuit Board Layout Example
      3. 12.2.3 PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DDW|44
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
PVDD Power-stage supply DC supply voltage 7 30 32 V
VDD(1) Supply voltage for internal LDO regulator to supply GVDD and AVDD DC supply voltage 7 32 V
External supply for VDD, GVDD and AVDD. Internal LDO bypassed DC supply voltage 4.5 5 5.5 V
AVDD Supply voltage for analog circuits DC supply voltage 4.5 5 5.5 V
GVDD Supply voltage for gate-drive circuitry DC supply voltage 4.5 5 5.5 V
RL(BTL) Load impedance PVDD = 30 V, Output filter inductance within recommended range 2.7 4 Ω
RL(PBTL) 1.6 3
LOUT(BTL) Output filter inductance Minimum output inductance at IOC 5 10 μH
LOUT(PBTL) Output filter inductance, PBTL before the LC filter Minimum output inductance at IOC 5 10
Output filter inductance, PBTL after the LC filter Minimum output inductance at half IOC , each inductor 5 10
FPWM PWM frame rate selectable for AM interference avoidance; 1% Resistor tolerance Nominal 575 600 625 kHz
AM1 510 533 555
AM2 460 480 500
R(FREQ_ADJ) PWM frame rate programming resistor Nominal; Master mode 49.5 50 50.5 kΩ
AM1; Master mode 29.7 30 30.3
AM2; Master mode 9.9 10 10.1
CPVDD PVDD close decoupling capacitors 1.0 μF
V(FREQ_ADJ) Voltage on FREQ_ADJ pin for slave mode operation Slave Mode (Connect to AVDD) 5 V
(1) VDD must be connected to a supply of 5V in LDO bypass mode; OR 7V to 30V with LDO active. VDD can be connected directly to PVDD in LDO active mode, but must not exceed PVDD voltage.