SLLSEU8B March   2017  – May 2020 TPD2S703-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      USB 2.0 Port With Short-to-Battery and IEC ESD Protection
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings—AEC Specification
    3. 6.3  ESD Ratings—IEC Specification
    4. 6.4  ESD Ratings—ISO Specification
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Thermal Information
    7. 6.7  Electrical Characteristics
    8. 6.8  Power Supply and Supply Current Consumption Chracteristics
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 OVP Operation
      2. 8.3.2 OVP Threshold
      3. 8.3.3 D± Clamping Voltage
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Device Operation
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Common choke and Inductor for VD+ and VD-
        2. 9.2.2.2 VREF Operation
          1. 9.2.2.2.1 Mode 0
          2. 9.2.2.2.2 Mode 1
        3. 9.2.2.3 Mode 1 Enable Timing
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 VPWR Path
    2. 10.2 VREF Pin
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.3 D± Clamping Voltage

The TPD2S703-Q1 provides a differentiated device architecture which allows the system designer to control the clamping voltage the protected transceiver sees from the D+ and D– pins. This architecture allows the system designer to minimize the amount of stress the transceiver sees during Short-to-Battery and ESD events. The clamping voltage that appears on the D+ and D– lines during a short-to-battery or ESD event obeys Equation 4.

Equation 4. TPD2S703-Q1 Equation_3.gif

Where VBR approximately = 0.7 V, IRDYN approximately = 1 V. By adjusting VREF, the clamping voltage of the D+ and D– lines can be adjusted. As VREF also controls the OVP threshold, take care to insure that the VREF setting both satisfies the OVP threshold requirements while simultaneously optimizing system protection on the D+ and D– lines.

The size of the capacitor used on the VREF pin also influences the clamping voltage as transient currents during Short-to-Battery and ESD events flow into the VREF capacitor. This causes the VREF voltage to increase, and likewise the clamping voltage on D± according to Equation 4. The larger capacitor that is used, the better the clamping performance of the device is going to be. See the parametric tables for the clamping performance of the TPD2S703-Q1 with a 1-µF capacitor.