SLLSEU8B March   2017  – May 2020 TPD2S703-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      USB 2.0 Port With Short-to-Battery and IEC ESD Protection
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings—AEC Specification
    3. 6.3  ESD Ratings—IEC Specification
    4. 6.4  ESD Ratings—ISO Specification
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Thermal Information
    7. 6.7  Electrical Characteristics
    8. 6.8  Power Supply and Supply Current Consumption Chracteristics
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 OVP Operation
      2. 8.3.2 OVP Threshold
      3. 8.3.3 D± Clamping Voltage
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Device Operation
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Common choke and Inductor for VD+ and VD-
        2. 9.2.2.2 VREF Operation
          1. 9.2.2.2.1 Mode 0
          2. 9.2.2.2.2 Mode 1
        3. 9.2.2.3 Mode 1 Enable Timing
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 VPWR Path
    2. 10.2 VREF Pin
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
VPWR 5-V DC supply voltage for internal circuitry 4.5 7 V
VREF Mode 0. Voltage range for VREF pin (for setting OVP threshold) 3 3.6 V
VREF Mode 1. Voltage range for VREF pin (for setting OVP threshold) 0.63 3.8 V
VD+, VD– Voltage range from connector-side USB data lines 0 3.6 V
D+, D– Voltage range for internal USB data lines 0 3.6 V
VEN Voltage range for enable 0 7 V
VFLT Voltage range for FLT 0 7 V
IFLT Current into open drain FLT pin FET 0 3 mA
CVPWR VPWR capacitance(1) VPWR pin 1 10 µF
CVREF VREF capacitance VREF pin 0.3 1 3 µF
CMODE Allowed parasitic capacitance on mode pin from PCB and mode 1 external resistors 20 pF
RMODE_0 Resistance to GND to set to mode 0 2 2.6 kΩ
RMODE_1 Resistance to GND to set to mode 1 (calculate parallel combination of RTOP and RBOT) 14 20 kΩ
(1) For recommended values for capacitors and resistors, the typical values assume a component placed on the board near the pin. Minimum and maximum values listed are inclusive of manufacturing tolerances, voltage derating, board capacitance, and temperature variation. The effective value presented should be within the minimum and maximums listed in the table.