SLLSEU8B March   2017  – May 2020 TPD2S703-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      USB 2.0 Port With Short-to-Battery and IEC ESD Protection
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings—AEC Specification
    3. 6.3  ESD Ratings—IEC Specification
    4. 6.4  ESD Ratings—ISO Specification
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Thermal Information
    7. 6.7  Electrical Characteristics
    8. 6.8  Power Supply and Supply Current Consumption Chracteristics
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 OVP Operation
      2. 8.3.2 OVP Threshold
      3. 8.3.3 D± Clamping Voltage
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Device Operation
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Common choke and Inductor for VD+ and VD-
        2. 9.2.2.2 VREF Operation
          1. 9.2.2.2.1 Mode 0
          2. 9.2.2.2.2 Mode 1
        3. 9.2.2.3 Mode 1 Enable Timing
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 VPWR Path
    2. 10.2 VREF Pin
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
MODE 1 ADJUSTABLE VREF
VMODE_CMP Mode 1 VREF feedback regulator voltage VMODE Standard mode 1 set-up. EN = 0 V. Once VREF = 3.3 V, measure voltage on mode pin 0.47 0.5 0.53 V
IMODE_LEAK Mode pin mode 1 leakage current IMODE Standard mode 1. Remove RTOP and RBOT. Power up device and wait until start-up time has passed. Then force 0.53 V on the MODE pin and measure current into pin 50 200 nA
VREF_ACCURACY VREF accuracy VREF Informative, test parameters below; accuracy with RTOP and RBOT as ±1% resistors –8% 8%
VREF_3.3V Mode 1 VREF set to 3.3 V VREF Standard mode 1 set-up. RTOP = 140 kΩ ± 1%, RBOT = 24.9 kΩ ± 1%. EN = 0. Measure value of VREF once it settles 3.04 3.31 3.58 V
VREF_0.66V Mode 1 VREF set to 0.66 V VREF Standard mode 1 set-up. RTOP = 47.5 kΩ ± 1%, RBOT = 150 kΩ ± 1%.EN = 0. Measure value of VREF once it settles 0.6 0.66 0.72 V
VREF_3.8V Mode 1 VREF set to 3.8 V VREF Standard mode 1 set-up. RTOP = 165 kΩ ± 1%, RBOT = 24.9 kΩ ± 1%. EN = 0. Measure value of VREF once it settles 3.5 3.81 4.12 V
EN, FLT PINS
VIH High-level input voltage EN Mode 0. Connect VPWR = 5 V; VREF = 3.3 V; VD+ = 3.3 V; Set VIH(EN) = 0 V; Sweep VIH from 0 V to 1.4 V; Measure when D+ drops low (less than or equal to 5% of 3.3 V) from 3.3 V 1.2 V
Low-level input voltage Mode 0. Connect VPWR = 5 V; VREF = 3.3 V; VD+ = 3.3 V. Set VIH(EN) = 3.3 V; Sweep VIH from 3.3 V to 0.5 V; Measure when D+ rise to 95% of 3.3 V from 0 V 0.8
IIL Input leakage current EN Mode 0. VPWR = 5 V; VREF = 3.3 V; VI (EN) = 3.3 V ; Measure current into EN pin 1 µA
VOL Low-level output voltage FLT Mode 0. Drive the TPS2S703-Q1 in OVP to assert FLT pin. Source IOL = 1 mA into FLT pin and measure voltage on FLT pin when asserted 0.4 V
TSD_RISING The rising over-temperature protection shutdown threshold VPWR = 5 V, ENZ = 0 V, TA stepped up until FLTZ is asserted 140 150 165 ℃
TSD_FALLING The falling over-temperature protection shutdown threshold VPWR = 5 V, ENZ = 0 V, TA stepped down from TSD_RISING until FLTZ is cleared 125 138 150 ℃
TSD_HYST The over-temperature protection shutdown threshold hysteresis TSD_RISING – TSD_FALLING 10 12 15 ℃
OVP CIRCUIT—VD±
VOVP_RISING Input overvoltage protection threshold, VREF > 3.6 V VD± Mode 1. Set VPWR = 5 V; EN = 0 V; RTOP = 165 kΩ, RBOT = 24.9 kΩ. Connect D± to 40-Ω load.  Increase VD+ or VD– from 4.1 V to 4.9 V. Measure the value at which FLTZ is asserted 4.3 4.5 4.7 V
VOVP_RISING Input overvoltage protection threshold VD± Mode 1. Set VPWR = 5 V; EN = 0 V; RTOP = 140 kΩ, RBOT = 24.9 kΩ. Increase VD+ or VD– from 3.6 V to 4.6 V. Measure the value at which FLTZ is asserted. Repeat for RTOP = 39 kΩ, RBOT = 150 kΩ. Increase VD+ or VD– from 0.6 V to 0.9 V. Measure the value at which FLTZ is asserted. See the resultant values meet the equation, and make sure to observe data switches turnoff.

Also check for mode 0 when VREF = 3.3 V		 1.19 × VREF 1.25 × VREF 1.31 × VREF V
VHYS_OVP Hysteresis on OVP VD± Difference between rising and falling OVP thresholds on VD± 25 mV
VOVP_FALLING Input overvoltage protection threshold VD± After collecting each rising OVP threshold, lower the VD± voltage until you see FLT deassert. This gives the falling OVP threshold. Use this value to calculate VHYS_OVP VOVP_RISING – VHYS_OVP V
IVD_LEAK_0 V Leakage current on VD± during normal operation VD± Standard mode 0 or mode 1. Set VD± = 0 V. D± = floating. Measure current flowing into VD± –0.1 0.1 µA
IVD_LEAK_3.6V Leakage current on VD± during normal operation VD± Standard mode 0 or mode 1. Set VD± = 3.6 V. D± = floating. Measure current flowing into VD± 2.5 4 µA
VOVP_3.3V Input overvoltage threshold for VREF = 3.3 V VD± Standard mode 1. RTOP = 140 kΩ ± 1%, RBOT = 24.9 kΩ ± 1%. Connect D± to 40-Ω load.  Measure the value at which FLTZ is asserted 3.61 4.14 4.67 V
VOVP_0.66V Input overvoltage threshold for VREF = 0.66 V VD± Standard mode 1. RTOP = 47.5 kΩ ± 1%, RBOT = 150 kΩ ± 1%. Connect D± to 40-Ω load. Measure the value at which FLTZ is asserted 0.72 0.83 0.94 V
SHORT-TO-BATTERY
VDATA_STB Data line hotplug short-to-battery tolerance V± Charge battery-equivalent capacitor to test voltage then discharge to pin under test through a 1 meter, 18-ga wire. (See Figure 23 application information for more details) 18 V
VCLAMP_STB_DP/M_3V3 Data line system side clamping voltage during STB D± Test both D+ and D– FETs. Test D+ and D– independently. Short VD+ and VD– to 18 V via hotplug to a battery-equivalent capacitor with a 1 meter, 18-ga wire. VREF = 3.3 V, VPWR = 5 V. Test in standard mode 0 and mode 1 5.5 6 V
VCLAMP_STB_DP/M_0V6 Data line system side clamping voltage during STB D± Test both D+ and D– FETs. Short VD+ and VD– to 18 V via hotplug to a battery-equivalent capacitor with a 1 meter, 18-ga wire. VREF = 0.63 V, VPWR = 5 V. Test in standard mode 0 and mode 1 3.2 3.5 V
DATA LINE SWITCHES – VD+ to D+ or VD– to D–
RON On resistance Mode 0 or 1. Set VPWR = 5 V; VREF = 3.3 V; EN = 0 V; Measure resistance between D+ and VD+ or D– and VD–, voltage between 0 and 0.4 V 4 6.5 Ω
RON(Flat) On resistance flatness Mode 0 or 1. Set VPWR = 5 V; VREF = 3.3 V; EN = 0 V; Measure resistance between D+ and VD+ or D– and VD–, sweep voltage between 0 and 0.4 V. Take difference of resistance at 0.4-V and 0-V VD± bias 1 Ω
BWON On bandwidth (–3-dB) Mode 0 or 1. Set VPWR = 5 V; VREF = 3.3 V; EN = 0 V; Measure S21 bandwidth from D+ to VD+ or D– to VD– with voltage swing = 400 mVpp, Vcm = 0.2 V 960 MHz