SLVSB97E July   2012  – January 2018 TPS23751 , TPS23752

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1. 3.1 Typical Application Circuit
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings: Surge
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electric Characteristics - Controller Section
    7. 6.7 Electrical Characteristics - Sleep Mode (TPS23752 Only)
    8. 6.8 Electrical Characteristics - PoE Interface Section
    9. 6.9 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Pin Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 PoE Overview
        1. 7.4.1.1 Threshold Voltages
        2. 7.4.1.2 PoE Startup Sequence
        3. 7.4.1.3 Detection
        4. 7.4.1.4 Hardware Classification
        5. 7.4.1.5 Inrush and Startup
        6. 7.4.1.6 Maintain Power Signature
        7. 7.4.1.7 Startup and Converter Operation
        8. 7.4.1.8 PD Hotswap Operation
      2. 7.4.2 Sleep Mode Operation (TPS23752 only)
        1. 7.4.2.1  Converter Controller Features
        2. 7.4.2.2  PWM and VFO Operation; CTL, SRT, and SRD Pin Relationships to Output Load Current
        3. 7.4.2.3  Bootstrap Topology
        4. 7.4.2.4  Current Slope Compensation and Current Limit
        5. 7.4.2.5  RT
        6. 7.4.2.6  T2P, Startup and Power Management
        7. 7.4.2.7  Thermal Shutdown
        8. 7.4.2.8  Adapter ORing
        9. 7.4.2.9  Using DEN to Disable PoE
        10. 7.4.2.10 ORing Challenges
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Input Bridges and Schottky Diodes
        2. 8.2.2.2  Protection, D1
        3. 8.2.2.3  Capacitor, C1
        4. 8.2.2.4  Detection Resistor, RDEN
        5. 8.2.2.5  Classification Resistor, RCLS
        6. 8.2.2.6  APD Pin Divider Network, RAPD1, RAPD2
        7. 8.2.2.7  Setting the PWM-VFO Threshold using the SRT pin
        8. 8.2.2.8  Setting Frequency (RT)
        9. 8.2.2.9  Current Slope Compensation
        10. 8.2.2.10 Voltage Feed-Forward Compensation
        11. 8.2.2.11 Estimating Bias Supply Requirements and Cvc
        12. 8.2.2.12 Switching Transformer Considerations and RVC
        13. 8.2.2.13 T2P Pin Interface
        14. 8.2.2.14 Softstart
        15. 8.2.2.15 Special Switching MOSFET Considerations
        16. 8.2.2.16 ESD
        17. 8.2.2.17 Thermal Considerations and OTSD
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

ORing Challenges

Preference of one power source presents a number of challenges. Combinations of adapter output voltage (nominal and tolerance), power insertion point, and which source is preferred determine solution complexity. Several factors adding to the complexity are the natural high-voltage selection of diode ORing (the simplest method of combining sources), the current limit implicit in the PSE, and PD inrush and protection circuits (necessary for operation and reliability). Creating simple and seamless solutions is difficult, if not impossible, for many of the combinations. However, the TPS23751 and TPS23752 offer several built-in features that simplify some combinations.

Several examples demonstrate the limitations inherent in ORing solutions. Diode ORing a 48 V adapter with PoE (option 1) presents the problem that either source may have the higher voltage. A blocking switch would be required to assure that one source dominates. A second example combines a 12 V adapter with PoE using option 2. The converter draws approximately four times the current at 12 V from the adapter than it does from PoE at 48 V. Transition from adapter power to PoE may demand more current than can be supplied by the PSE. The converter must be turned off while the CIN capacitance charges, with a subsequent converter restart at the higher voltage and lower input current. A third example involves the loss of the MPS when running from the adapter, causing the PSE to remove power from the PD. If ac power is then lost, the PD stops operating until the PSE detects and powers the PD.