SLVS727E November   2006  – October 2019 TPS2410 , TPS2411


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application Diagram
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
    1.     Pin Functions, PW
    2.     Pin Functions, RMS
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: TPS2410, 11
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Pins
        1.  A, C:
        2.  BYP:
        3.  FLTR:
        4.  FLTB:
        5.  GATE:
        6.  GND:
        7.  RSET:
        8.  RSVD:
        9.  STAT
        10. UV, OV, PG:
        11. VDD:
      2. 8.3.2 Gate Drive, Charge Pump and C(BYP)
      3. 8.3.3 Fast Comparator Input Filtering – C(FLTR)
      4. 8.3.4 UV, OV, and PG
      5. 8.3.5 Input ORing and Stat
    4. 8.4 Device Functional Modes
      1. 8.4.1 TPS2410 vs TPS2411 – MOSFET Control Methods
  9. Application and Implementation
    1. 9.1 Typical Connections
      1. 9.1.1 N+1 Power Supply
      2. 9.1.2 Input ORing
    2. 9.2 Typical Application Examples
      1. 9.2.1 VDD, BYP, and Powering Options
      2. 9.2.2 Bidirectional Blocking and Protection of C
      3. 9.2.3 ORing Examples
      4. 9.2.4 Design Requirements
        1. MOSFET Selection and R(RSET)
        2. TPS2410 Regulation-loop Stability
      5. 9.2.5 Detailed Design Procedure
      6. 9.2.6 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Recommended Operating Range
    2. 10.2 System Design and Behavior with Transients
  11. 11Layout
    1. 11.1 Layout Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Input ORing and Stat

STAT provides information regarding the state of the MOSFET gate drive. STAT is pulled to VDD, through a 46-kΩ internal pullup, if GATE is being driven high and V(GATE) exceeds V(A) plus 0.4 V. The STAT pin may be directly connected to low-voltage logic by using the logic gate input ESD clamp to control the voltage or by using a much lower pullup resistor (that is, 5 kΩ) to the logic supply voltage. STAT must be allowed to rise above VDD/2 to avoid effecting the reverse turn-off threshold.

Interconnecting STAT pins can be used to reduce the occurrence of both MOSFETs turning off in topologies such as Figure 11 that normally have both MOSFETs ON. This might occur when there is a noise transient on both buses due to fans cycling on and off, or an ac mains disturbance. If both MOSFETs are ON, and then an ORing circuit turns OFF, the second ORing circuit fast turnoff threshold is shifted negative by 157 mV from the RSET programmed value because STAT is pulled low. This reduces the probability that it too turns off as the arrival of the transient, and speed of both circuits, is unlikely to be matched. Maintaining at least one device ON avoids both a bus transient due to the current interruption, and momentary downstream hotswap overload when the ORing recovers. The function of STAT is not limited to the topology of Figure 11 and may be used to dynamically shift the fast turnoff threshold. The internal circuit shown in the FUNCTIONAL BLOCK DIAGRAM assists in designing these applications.

Figure 8 shows how STAT and OV can be used to latch the TPS2410 off. This is useful when a system operation benefits from preventing a failed power module from repeatedly disturbing the bus, and may be used in conjunction with back-to-back MOSFETs. The OV pin must be help low until V(GATE) is 0.4 V above V(A) in order to accomplish a reset.

TPS2410 TPS2411 use_latch_lvs727.gifFigure 8. Use of STAT and OV to Latch TPS2411 OFF