SLVSHM3 November 2026 TPS2HCS05-Q1

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slvshm3_oa

9 TPS2HCS05-Q1 Registers

Table 9-1 lists the memory-mapped registers for the TPS2HCS05-Q1 registers. All register offset addresses not listed in Table 9-1 should be considered as reserved locations and the register contents should not be modified.

Table 9-1 TPS2HCS05-Q1 Registers

Offset	Acronym	Register Name	Section
0h	DEV_ID	Read the device ID from NVM, can not be reconfigured through user EEPROM	Go
1h	SLEEP	Sets to go into SLEEP sate from ACTIVE or STANDBY state	Go
2h	LPM	Sets to go in or out of Low power mode (LPM STATE)	Go
3h	GLOBAL_FAULT_TYPE	Faults for any channel and global faults	Go
4h	FAULT_MASK	Mask the reporting of the faults on the fault pin	Go
6h	SW_STATE	Turn on/off OUTx	Go
8h	DEV_CONFIG	Device Configuration register	Go
9h	ADC_CONFIG	ADC configuration - disable ADC conversions or ADC entirely	Go
Ah	ADC_RESULT_VBB	ADC conversion result VBB	Go
Ch	FLT_STAT_CH1	Status of the channels and channel faults	Go
Dh	PWM_CH1	Set all PWM configurations for channel 1	Go
Eh	ILIM_CONFIG_CH1	Set all current limit configuration for channel 1	Go
Fh	CH1_CONFIG	Configuration register for channel 1	Go
10h	ADC_RESULT_CH1_I	ADC conversion result load current sense CH1	Go
11h	ADC_RESULT_CH1_T	ADC conversion result TJ sense CH1	Go
12h	ADC_RESULT_CH1_V	ADC conversion result VOUT sense CH1	Go
13h	ADC_RESULT_CH1_VDS	ADC conversion result VDS sense CH1	Go
14h	I2T_CONFIG_CH1	Set all I2T configuration bits	Go
15h	FLT_STAT_CH2	Status of the channels and channel faults	Go
16h	PWM_CH2	Set all PWM configurations for channel 2	Go
17h	ILIM_CONFIG_CH2	Set all current limit configuration for channel 2	Go
18h	CH2_CONFIG	Configuration register for channel 2	Go
19h	ADC_RESULT_CH2_I	ADC conversion result load current sense CH2	Go
1Ah	ADC_RESULT_CH2_T	ADC conversion result TJ sense CH2	Go
1Bh	ADC_RESULT_CH2_V	ADC conversion result VOUT sense CH2	Go
1Ch	ADC_RESULT_CH2_VDS	ADC conversion result VDS sense CH2	Go
1Dh	I2T_CONFIG_CH2	Set all I2T configuration bits	Go
3Fh	EEPROM_PROG	Customer EEPROM program control and status register	Go
50h	TSNS_CAL_RESULT_CH1	ADC calibration result for TSNS for CH1	Go
51h	TSNS_CAL_RESULT_CH2	ADC calibration result for TSNS for CH2	Go
52h	CUST_REG_52	Customer defined programmable register	Go
53h	CUST_REG_53	Customer defined programmable register	Go
54h	CUST_REG_54	Customer defined programmable register	Go
55h	CUST_REG_55	Customer defined programmable register	Go
56h	CUST_REG_56	Customer defined programmable register	Go
57h	CUST_REG_57	Customer defined programmable register	Go

Complex bit access types are encoded to fit into small table cells. Table 9-2 shows the codes that are used for access types in this section.

Table 9-2 TPS2HCS05-Q1 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
RC	R C	Read to Clear
Write Type
W	W	Write
W1C	W 1C	Write 1 to clear
Reset or Default Value
-n		Value after reset or the default value

9.1 DEV_ID Register (Offset = 0h) [Reset = XXXXh]

DEV_ID is shown in Table 9-3.

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Table 9-3 DEV_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	DEV_ID	R	X	Part Number FF00h = TPS2HCS05A-Q1 FF01h = TPS2HCS05B-Q1

9.2 SLEEP Register (Offset = 1h) [Reset = FFFEh]

SLEEP is shown in Table 9-4.

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Table 9-4 SLEEP Register Field Descriptions

Bit	Field	Type	Reset	Description
15-1	RESERVED	R	7FFFh	Reserved
0	SLEEP	R/W	0h	Set this bit to 1 to send the device to SLEEP state 0h = No change 1h = Sends the device to SLEEP state

9.3 LPM Register (Offset = 2h) [Reset = FF00h]

LPM is shown in Table 9-5.

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Table 9-5 LPM Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	FFh	Reserved
7-6	MAN_LPM_EXIT_CURR_CH2	R/W	0h	Set the threshold to exit from MANUAL_LPM mode due to load current increase - CH2 Depending on the MANUAL_LPM_MODE setting the thresholds for the exit will be different. If MANUAL_LPM_MODE = 0, the thresholds are: 0b00 = 0.95A 0b01 = 1.2A 0b10 = 0.33A 0b11 = 0.64A If MANUAL_LPM_MODE = 1, the thresholds are: 0h = 3.1A 1h = 4.1A 2h = 1A 3h = 2A
5-4	MAN_LPM_EXIT_CURR_CH1	R/W	0h	Set the threshold to exit from MANUAL_LPM mode due to load current increase - CH1 Depending on the MANUAL_LPM_MODE setting the thresholds for the exit will be different. If MANUAL_LPM_MODE = 0, the thresholds are: 0b00 = 0.95A 0b01 = 1.2A 0b10 = 0.33A 0b11 = 0.64A If MANUAL_LPM_MODE = 1, the thresholds are: 0h = 3.1A 1h = 4.1A 2h = 1A 3h = 2A
3	AUTO_LPM_EXIT_CH2	R/W	0h	This bit forces the device out of AUTO_LPM mode to ACTIVE state and enables CH2 if not already enabled. To re-enable the device to enter AUTO_LPM mode this bit must be set back to 0. 0h = Re-enables device to enter AUTO_LPM mode if all conditions are met 1h = Forces an exit from AUTO_LPM state to ACTIVE state. Enable CH2 if not already enabled
2	AUTO_LPM_EXIT_CH1	R/W	0h	This bit forces the device out of AUTO_LPM mode to ACTIVE state and enables CH1 if not already enabled. To re-enable the device to enter AUTO_LPM mode this bit must be set back to 0. 0h = Re-enables device to enter AUTO_LPM mode if all conditions are met 1h = Forces an exit from AUTO_LPM state to ACTIVE state. Enable CH1 if not already enabled
1	MANUAL_LPM_MODE	R/W	0h	The bit determines if the large or small internal FET should be used for both channels when the device is in MANUAL_LPM mode 0h = Smaller internal FET is used, higher RON, lower exit threshold currents 1h = Larger internal FET is used, lower RON, higher exit threshold currents
0	MANUAL_LPM_ENTRY	R/W	0h	Setting this bit to 1 puts the device into MANUAL_LPM. Note: Both channels must be off or the current on any enabled channel(s) must be below MAN_LPM_EXIT_CURR_CHx to enter MANUAL_LPM mode. If the device is in MANUAL_LPM state and a 0 is written to the MANUAL_LPM_ENTRY bit the device will look at the contents of AUTO_LPM_EXIT_CHx bits and if any of the bits are set to 1 the device will exit MANUAL_LPM mode and will turn on the channel(s) if not already enabled. If the device exits MANUAL_LPM state to ACTIVE state due to a load current increase > MAN_LPM_EXIT_CURR_CHx, the MANUAL_LPM_ENTRY bit needs to be set 0 and then back to 1 to re-enter MANUAL_LPM state 0h = Sends the device to ACTIVE mode if device is in MANUAL_LPM 1h = Sends the device to MANUAL_LPM mode if all conditions are met

9.4 GLOBAL_FAULT_TYPE Register (Offset = 3h) [Reset = 0147h]

GLOBAL_FAULT_TYPE is shown in Table 9-6.

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Table 9-6 GLOBAL_FAULT_TYPE Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	CH2_FLT	R	0h	Fault status of channel 2. If FLT_LTCH_DIS = 0, then the fault bit is latched and is cleared only when the FLT_STAT_CH2 register is read and the fault condition(s) no longer exist If FLT_LTCH_DIS = 1, then the fault bit is cleared when the fault condition(s) no longer exist 0h = No fault(s) have occurred on CH2 1h = Fault(s) have occurred on CH2
12	CH1_FLT	R	0h	Fault status of channel 1. If FLT_LTCH_DIS = 0, then the fault bit is latched and is cleared only when the FLT_STAT_CH1 register is read and the fault condition(s) no longer exist If FLT_LTCH_DIS = 1, then the fault bit is cleared when the fault condition(s) no longer exist 0h = No fault(s) have occurred on CH1 1h = Fault(s) have occurred on CH1
11	LPM_STATUS	R	0h	The bit indicates if the device is in either MANUAL_LPM mode or AUTO_LPM mode and is cleared when the device is not in any LPM mode. 0h = Device is not in the AUTO_LPM or MANUAL_LPM state 1h = Device has entered either AUTO_LPM or MANUAL_LPM state
10	CHAN_OCP_I2T_TSD	R	0h	This bit indicates if there is an overcurrent protection or I2T protection or thermal shutdown fault in any one of the channels. If FLT_LTCH_DIS = 0, then the fault bit is latched and is cleared only when the FLT_STAT_CHx register is read and the fault condition(s) no longer exist If FLT_LTCH_DIS = 1, then the fault bit is cleared when the fault condition(s) no longer exist 0h = No overcurrent protection, I2T protection, or thermal shutdown fault in any of the channels 1h = Overcurrent protection, I2T protection, or thermal shutdown fault(s) in one or both of the channels
9	OL_SHRT_VBB_OFF_FLT	R	0h	This bit indicates if there is a short to VBB supply in the off-state fault in any one of the channels. If FLT_LTCH_DIS = 0, then the fault bit is latched and is cleared only when the FLT_STAT_CHx register is read and the fault condition(s) no longer exist If FLT_LTCH_DIS = 1, then the fault bit is cleared when the fault condition(s) no longer exist 0h = No off-state short to VBB or open load fault in any of the channels 1h = Off-state short to VBB or open load fault(s) in one or both of the channels
8	GLOBAL_ERR_WRN	R	1h	This bit indicates if there is a global fault reported in FLT_GLOBAL_TYPE[7:0] bits. The faults that are reported through this bit are LIMPHOME_STATE, POR, SPI_ERR, WD_ERR, VDD_UVLO, VBB_UV_WRN, or VBB_UVLO. If FLT_LTCH_DIS = 0, then the fault bit is latched and is cleared only when the GLOBAL_FAULT_TYPE register is read and the fault condition(s) no longer exist If FLT_LTCH_DIS = 1, then the fault bit is cleared when the fault condition(s) no longer exist 0h = No global fault has occurred 1h = One of the following event(s) have occurred: LIMPHOME_STATE, POR, SPI_ERR, WD_ERR, VDD_UVLO, VBB_UV_WRN, or VBB_UVLO
7	LIMPHOME_STAT	R/W1C	0h	This bit indicates if the device is in LIMP_HOME state as a result of the LHI pin going high. Write 1 to clear and exit LIMP_HOME state. The LHI pin must be LOW when the bit is set to 1 to exit LIMP_HOME state. 0h = Device is not in LIMP_HOME state 1h = Device is in LIMP_HOME state due to LHI pin going high
6	POR	RC	1h	The bit is indicates if a power on reset (POR) has occurred since the last read This bit is cleared on read, so if read again and the bit is 0, this means that no power-on reset has occurred since the read. 0h = No power on reset (POR) has occured since the last register read 1h = A power-on reset has occurred since the last register read.
5	LPM_STATUS_1	RC	0h	This bit indicates if the device is in either MANUAL_LPM or AUTO_LPM modes. This bit is latched and cleared only when read and the device is not in any LPM mode. Note: If the conditons are not met for MANUAL_LPM entry, this bit will be set to 1 and cleared when read. 0h = Device is not in the AUTO_LPM or MANUAL_LPM state 1h = Device has entered either AUTO_LPM or MANUAL_LPM state
4	SPI_ERR	RC	0h	This bit indicates if there is a SPI communication error either from format, clock or CRC. The fault bit is latched and cleared only after read and the error(s) no longer exist. 0h = No SPI communication error(s) fault have occurred 1h = SPI communication error either from format, clock or CRC has occurred
3	WD_ERR	RC	0h	If WD_EN = 1, this bit indicates if there has not been an acceptable SPI command in the watchdog timeout window. The fault bit is latched and cleared only after read and the error no longer exists 0h = No SPI interface watchdog error 1h = SPI watchdog timeout error has occurred
2	VDD_UVLO	RC	1h	This bit indicates if the VDD supply is below VDD_UVLOF at any time. The fault bit is cleared if the GLOBAL_FAULT_TYPE register is read and the UVLO condition is removed 0h = No VDD_UVLO fault has occurred 1h = VDD_UVLO fault has occurred
1	VBB_UV_WRN	RC	1h	This bit indicates if the VBB supply is below the V_{BB_UV_WRN} at any time. If VBB is below V_{BB_UV_WRN}, the diagnostics in the device are turned off The fault bit is cleared if the GLOBAL_FAULT_TYPE register is read and the UV condition no longer exists 0h = No VBB_UV_WRN fault has occurred 1h = VBB_UV_WRN fault has occurred
0	VBB_UVLO	RC	1h	This bit indicates if the VBB supply is below the V_{BB_UVLOF} at any time. The fault bit is cleared if the GLOBAL_FAULT_TYPE register is read and the UVLO condition is removed 0h = No VBB_UVLO fault has occurred 1h = VBB_UVLO fault has occurred

9.5 FAULT_MASK Register (Offset = 4h) [Reset = XXXXh]

FAULT_MASK is shown in Table 9-7.

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Table 9-7 FAULT_MASK Register Field Descriptions

Bit	Field	Type	Reset	Description
15-7	RESERVED	R	X	Reserved
6	RESERVED	R/W	X	Reserved
5	MASK_SHRT_VBB	R/W	X	This bit determines if the device should mask the signaling of an off-state short-to-battery fault on the FLT pin 0h = Short to VBB fault is signaled on the FLT pin 1h = Short to VBB fault is not signaled (masked from) on the FLT pin
4	MASK_OL_OFF	R/W	X	The bit determines if the device should mask the signaling of an off-state open load fault on the FLT pin 0h = Off-state wire-break fault is signaled on the FLT pin on detecting the fault with the diagnostic 1h = Off-state wire-break fault is not signaled (masked from) on the FLT pin
3	RESERVED	R	X	Reserved
2	MASK_SPI_ERR	R/W	X	The bit determines if the device should mask a SPI error (SPI_ERR) on the FLT pin and in the GLOBAL_FAULT_TYPE register 0h = SPI error is signaled on the FLT pin and in the GLOBAL_FAULT_TYPE register 1h = SPI error is not signaled on the FLT pin or in the GLOBAL_FAULT_TYPE register
1	MASK_WD_ERR	R/W	X	The bit determines if the device should mask a SPI watchdog error (WD_ERR) on the FLT pin and in the GLOBAL_FAULT_TYPE register 0h = SPI watchdog error is signaled on the FLT pin and in the GLOBAL_FAULT_TYPE register 1h = SPI watchdog error is not signaled on the FLT pin or in the GLOBAL_FAULT_TYPE register
0	MASK_VBB_UVLO	R/W	X	The bit determines if the device should mask the supply voltage VBB UVLO fault on the FLT pin 0h = VBB_UVLO fault is signaled on the FLT pin 1h = VBB_UVLO fault is not signaled (masked from) on the FLT pin

9.6 SW_STATE Register (Offset = 6h) [Reset = FFFCh]

SW_STATE is shown in Table 9-8.

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Table 9-8 SW_STATE Register Field Descriptions

Bit	Field	Type	Reset	Description
15-2	RESERVED	R	3FFFh	Reserved
1	CH2_ON	R/W	0h	This bit determines the output state of channel 2 for TPS2HCS05A-Q1 versions. 0h = CH2 Output set to OFF (FET is OFF) 1h = CH2 Output set to ON (FET is ON) Note: This bit has no effect on TPS2HCS05B-Q1. For TPS2HCS05B-Q1, control of channel 2 output is determined only through the DI2 pin.
0	CH1_ON	R/W	0h	This bit determines the output state of channel 1 for TPS2HCS05A-Q1 versions. 0h = CH1 Output set to OFF (FET is OFF) 1h = CH1 Output set to ON (FET is ON) Note: This bit has no effect on TPS2HCS05B-Q1 version. For TPS2HCS05B-Q1, control of channel 1 output is determined only through the DI1 pin

9.7 DEV_CONFIG Register (Offset = 8h) [Reset = XXXXh]

DEV_CONFIG is shown in Table 9-9.

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Table 9-9 DEV_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	CRC_EN	R/W	X	Set this bit to 1 to enable CRC check of SPI command frame. 0h = No CRC check of SPI command frame 1h = CRC check of SPI command frame enabled
14-13	RESERVED	R/W	X	Reserved
12-11	RESERVED	R/W	X	Reserved
10-9	CH2_LH_IN	R/W	X	These bits determine how the channel 2 output should respond in LIMP_HOME state for the TPS2HCS05A-Q1 versions. Note: These bits have no effect on TPS2HCS05B-Q1. There is no LIMP_HOME state for TPS2HCS05B-Q1. If DI_OUT_DIS_FN = 0, the values are: 0h = DI pin controls the output when in LIMP_HOME state 1h = Keeps the same output state from CH2_ON bit when entering LIMP_HOME state 2h = Output will be OFF in LIMP_HOME mode 3h = Output will be ON in LIMP_HOME mode If DI_OUT_DIS_FN = 1, the values are: 0h = Output will be OFF in LIMP_HOME mode 1h = Keeps the same output state from CH2_ON bit when entering LIMP_HOME state 2h = Output will be OFF in LIMP_HOME mode 3h = Output will be ON in LIMP_HOME mode
8-7	CH1_LH_IN	R/W	X	These bits determine how the channel 1 output should respond in LIMP_HOME state for the TPS2HCS05A-Q1 versions. Note: These bits have no effect on TPS2HCS05B-Q1. There is no LIMP_HOME state for TPS2HCS05B-Q1. If DI_OUT_DIS_FN = 0, the values are: 0h = DI pin controls the output when in LIMP_HOME state 1h = Keeps the same output state from CH1_ON bit when entering LIMP_HOME state 2h = Output will be OFF in LIMP_HOME mode 3h = Output will be ON in LIMP_HOME mode If DI_OUT_DIS_FN = 1, the values are: 0h = Output will be OFF in LIMP_HOME mode 1h = Keeps the same output state from CH1_ON bit when entering LIMP_HOME state 2h = Output will be OFF in LIMP_HOME mode 3h = Output will be ON in LIMP_HOME mode
6	DI_OUT_DIS_FN	R/W	X	Set this bit to 1 to use the DI / OUT_DIS pin (pin 5) as a fast output disable 0h = The LH state is determined by a DI_OUT_DIS pin (DI pin function) 1h = Outputs are disabled when DI_OUT_DIS pin is set HI (OUT_DIS function)
5	AUTO_LPM_ENTRY	R/W	X	This bit determines if the device should enter AUTO_LPM mode if all the conditions are met to enter AUTO_LPM mode. 0h = Entry into AUTO_LPM mode is disabled 1h = Entry into AUTO_LPM mode is enabled and the device enters if all the conditions are met to enter
4	RESERVED	R/W	0h	This bit should always be programmed and set to 0 If this bit is set to 1 and AUTO_LPM_ENTRY = 1, the device will be able to enter AUTO_LPM even if VSNS_DIS_CH2=0 and/or VDSSNS_DIS_CH2=0.
3	WD_EN	R/W	X	The bit determines if the SPI watchdog function is enabled. If enabled, the watchdog timout triggers if there is not a valid SPI command in the watchdog timeout window 0h = Watchdog is disabled 1h = Watchdog function is enabled
2-1	WD_TO	R/W	X	This bit determines the timeout period for the SPI watchdog function (if enabled). The watchdog timeout triggers if there is not a valid SPI command in the watchdog timeout window. 0h = Watchdog timeout period is 400µs 1h = Watchdog timeout period is 400ms 2h = Watchdog timeout period is 800ms 3h = Watchdog timeout period is 1200ms
0	FLT_LTCH_DIS	R/W	X	This bit determines if the fault bits in FAULT_GLOBAL_TYPE [13:8] should latch if a fault occurs. 0h = Fault bits [13:8] in FAULT_GLOBAL_TYPE register latched and cleared only on read of the associated register 1h = Fault bits [13:8] in FAULT_GLOBAL_TYPE register are not latched and are cleared when the fault no longer exists Note: See each fault bit description for more details on how to clear the individual fault bits when FLT_LTCH_DIS = 0. LPM_STATUS[0] is read only.

9.8 ADC_CONFIG Register (Offset = 9h) [Reset = FF3Ah]

ADC_CONFIG is shown in Table 9-10.

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Table 9-10 ADC_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	FFh	Reserved
7-6	ADC_ISNS_SAMPLE_CONFIG	R/W	0h	These bits determine the sampling and conversion rate for the current sense (ISNS). The slower the sampling and conversion rate the lower the IQ consumption. 0h = Current sense and ADC conversion at max rate 1h = Current sense and ADC conversion at max rate 2h = Current sense and ADC conversion at one half max rate 3h = Current sense and ADC conversion at one quarter max rate
5	ADC_VDS_DIS	R/W	1h	This bit determines if the VDS sense funciton should be disabled for all channels. If disabled, this excludes VDS conversion for all channels in the ADC conversion sequence. Note: The VDS sense function can also be enabled or disabled per channel through the VDS_SNS_DIS_CHx bit in the DIAG_CONFIG_CHx register. This bit must be set to 0 to enable/disable the function on a channel basis. 0h = VDS_SNS ADC function is enabled 1h = VDS SNS ADC functionality is disabled for all channels, VDS_SNS ADC conversion is excluded in the ADC conversion sequence for all channels
4	ADC_VSNS_DIS	R/W	1h	This bit determines if the VOUT sense (VSNS) funciton should be disabled for all channels. If disabled, this excludes the VOUT conversion for all channels in the ADC conversion sequence. Note: The VSNS function can also be enabled or disabled per channel through the VSNS_DIS_CHx bit in the DIAG_CONFIG_CHx register. This bit must be set to 0 to enable/disable the function on a channel basis. 0h = VSNS ADC function is enabled 1h = VSNS ADC functionality is disabled for all channels, VSNS ADC conversion is excluded in the ADC conversion sequence for all channels
3	ADC_TSNS_DIS	R/W	1h	This bit determines if the temperature sense function is disabled for all channels. If disabled, this excludes the temperature sense conversion for all channels in the ADC conversion sequence. Note: The temperature sense function can only be enabled or disabled globally 0h = TSNS ADC function is enabled 1h = TSNS ADC functionality is disabled for all channels, TSNS ADC conversion is excluded in the ADC conversion sequence for all channels
2	ADC_ISNS_DIS	R/W	0h	This bit determines if the current sense (ISNS) function is disabled for all channels. If disabled, this excludes the ISNS conversion for all channels in the ADC conversion sequence Note: The ISNS function can also be enabled or disabled per channel through the ISNS_DIS_CHx in DIAG_CONFIG_CHx register. This bit must be set to 0 to enable/disable the function on a channel basis. 0h = ISNS ADC function is enabled 1h = ISNS ADC functionality is disabled for all channels, ISNS ADC conversion is excluded in the ADC conversion sequence for all channels
1	ADC_VBB_DIS	R/W	1h	This bit determines if the VBB_SNS function is disabled. If disabled, this excludes supply voltage VBB conversion in the ADC conversion sequence. 0h = VBB_SNS ADC function is enabled, VBB_SNS ADC conversion is included in the ADC conversion sequence 1h = VBB_SNS ADC function is disabled, VBB_SNS ADC conversion is excluded in the ADC conversion sequence
0	ADC_DIS	R/W	0h	This bit determines if the ADC function should be disabled. If disabled, no VDS_SNS, VSNS, TSNS, or ISNS is possible. The ADC is enabled by default. 0h = ADC function enabled 1h = All ADC functions disabled

9.9 ADC_RESULT_VBB Register (Offset = Ah) [Reset = F800h]

ADC_RESULT_VBB is shown in Table 9-11.

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Table 9-11 ADC_RESULT_VBB Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	1Fh	Reserved
10	VBB_RDY	R	0h	This bit indicates if a new ADC result for VBB voltage conversion is available since the last read 0h = VBB ADC value not updated 1h = New VBB ADC value ready since last read
9-0	ADC_RESULT_VBB	R	0h	10-bit ADC result from the conversion of the VBB voltage

9.10 FLT_STAT_CH1 Register (Offset = Ch) [Reset = E000h]

FLT_STAT_CH1 is shown in Table 9-12.

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Table 9-12 FLT_STAT_CH1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	7h	Reserved
12	I2T_MOD_CH1	R	0h	This bit indicates if channel 1 in the I2T loop and is accumulating. When channel 1 is not in the I2T loop the value will be 0 0h = I2T is off or the channel is not in the I2T loop 1h = Channel is in the I2T loop and is accumulating
11	LATCH_STAT_CH1	RC	0h	This bit indicates if channel 1 has been latch off due to an overcurrent protection or thermal shutdown fault. The bit clears when the channel is toggled off and back on. Note: This bit does not signal when a shutdown occurs due to I2T 0h = This channel is not latched off 1h = This channel is currently latched off
10	FLT_CH1	R	0h	This bit indicates if channel 1 is currently in an auto retry wait time period, latched off, or in I2T cooldown 0h = This channel is currently not in auto retry wait time, latched off state, or I2T cooldown 1h = This channel is currently in auto retry wait time, latched off state, or I2T cooldown
9	SW_STATE_STAT_CH1	R	0h	This bit indicates the current state of channel 1 no matter which mode the device is in as long as SPI is functioning 0h = CH1 is OFF 1h = CH1 is ON
8	VOUT_ERR_CH1	R	0h	This bit indicates if the drain-to-source voltage (V_DS) of channel 1 < V_{DS_LT_2V} after the channel is enabled and is out of the inrush period (if configured) for t > t_{VDS_DEGL}. 0h = The VDS voltage is correct (< 2V) when this channel is enabled 1h = The VDS voltage is incorrect (> 2V) when this channel is supposed to be enabled
7	I2T_FLT_CH1	RC	0h	This bit indicates if an I2T fault has occured on channel 1. I2T_EN must be set to 1 in order for this bit indicate an I2T fault. The fault is latched and cleared when FLT_STAT_CH1 register is read and the fault condition no longer exists Note: This bit does not indicate an overcurrent protection or thermal shutdown fault 0h = no I2T fault has occurred or I2T is not enabled 1h = I2T fault has occurred on this channel
6	LPM_WAKE_CH1	R	0h	This bit indicates if channel 1 was the cause for the device to come out of AUTO_LPM or MANUAL_LPM regardless of the cause (load step, short-circuit) 0h = The device was not in LPM or this channel was not the cause the device came out of AUTO_LPM or MANUAL_LPM mode 1h = This channel was the reason the device came out of AUTO_LPM or MANUAL_LPM
5	THERMAL_SD_CH1	RC	0h	This bit indicates if thermal shutdown fault has occurred on channel 1. The fault is latched and cleared when the FLT_STAT_CH1 register is read and the retry timer has expired and the channel temperature has fallen below the thermal shutdown hysteresis threshold 0h = No thermal shutdown fault has occurred on this channel 1h = A thermal shutdown fault has occurred on this channel
4	ILIMIT_CH1	RC	0h	This bit indicates if an overcurrent protection fault has occurred on channel 1 The fault is latched and cleared when FLT_STAT_CH1 register is read and the fault condition no longer exists 0h = No overcurrent protection fault has occurred on this channel 1h = Overcurrent protection fault has occurred on this channel
3	SHRT_VBB_CH1	RC	0h	This bit indicates if there was a short to VBB in the off-state on channel 1. The fault is latched and cleared when FLT_STAT_CH1 register is read and the fault condition no longer exists Note: SVBB_EN_CH1 must be enabled for this bit to signal short to VBB in the off state. 0h = No Short to VBB fault in off-state has occurred on this channel or short to VBB in off-state is not enabled 1h = Short to VBB fault in the off-state has occurred on this channel
2	OL_OFF_CH1	R	0h	This bit indicates if there is an open load in the off-state on channel 1. The output of channel 1 is pulled up by the OL_PULLUP_STR setting. Note: OL_OFF_EN_CH1 must be enabled for this bit to signal an open load in the off-state. 0h = No off-state open load fault has occurred on this channel or off-state open load detection in off-state is not enabled 1h = Off-state open load fault has occurred on this channel
1	RESERVED	R	0h	Reserved
0	THERMAL_WRN_CH1	RC	0h	This bit indicates if the channel 1 FET temperature is above the overtemperature warning threshold. The fault is latched and cleared when FLT_STAT_CH1 register is read and the fault condition no longer exists 0h = FET temperature is below the over-temperature warning threshold in this channel 1h = FET temperature is above the over-temperature warning threshold in this channel

9.11 PWM_CH1 Register (Offset = Dh) [Reset = F000h]

PWM_CH1 is shown in Table 9-13.

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Table 9-13 PWM_CH1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	Fh	Reserved
11-9	PWM_FREQ_CH1	R/W	0h	Set the PWM frequency 0h = 0.86Hz 1h = 3.5Hz 2h = 14Hz 3h = 112Hz 4h = 224Hz 5h = 448Hz 6h = 895Hz 7h = 1765Hz
8-1	PWM_DTY_CH1	R/W	0h	These bits are used to set the duty cycle for the PWM operation for channel 1. Each bit is ~0.39% duty cycle, linearly up to 100% duty cycle
0	PWM_EN_CH1	R/W	0h	This bit enables PWM operation of channel 1. Note: The duty cycle of PWM > 200us. If fault will occur in FLT_STAT_CH1 register. PWM mode can only be enabled if CAP_CHRG_CH1[1:0] = 0 0h = Output follows CH1_ON setting 1h = Output is PWM according to duty cycle and frequency set if CH1_ON is high

9.12 ILIM_CONFIG_CH1 Register (Offset = Eh) [Reset = XXXXh]

ILIM_CONFIG_CH1 is shown in Table 9-14.

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Table 9-14 ILIM_CONFIG_CH1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R/W	X	Reserved
13-12	CAP_CHRG_CH1	R/W	X	These bits set the capacitive charging mode during the inrush period after turn on. When CAP_CHRG_CH1 = 00, these are bits are programmed as the overcurrent protection threshold during the INRUSH_DURATION_CH1 period. The channel will immediately turn off if the threshold is reached. When CAP_CHRG_CH1 = 10, these bits are programmed as the current limit regulation threshold. The channel will turn on into the current limit and will continue to regulate the current until the output is fully charged or there is a thermal shutdown event. Note: PWM and I2T is not enabled during the INRUSH_DURATION. 0h = No cap charging mode, IOCP value set by INRUSH_LIMIT_CH1 bits 1h = Not supported 2h = Current limit regulation mode, value set by INRUSH_LIMIT_CH1 bits 3h = Not supported
11	I2T_EN_CH1	R/W	X	Enables the I2T functionality for channel 1. I2T can be enabled before the channel is enabled or while it is enabled, but the I2T calculation will only start after the inrush period ends. 0h = I2T functionality not enabled 1h = I2T functionality is enabled
10-8	INRUSH_DURATION_CH1	R/W	X	These bits determine the inrush period duration during which the INRUSH_LIMIT_CH1 level applies. 0h = 0ms 1h = 2ms 2h = 4ms 3h = 6ms 4h = 10ms 5h = 20ms 6h = 50ms 7h = 100ms
7-4	INRUSH_LIMIT_CH1	R/W	X	These bits determine the inrush current limit on channel 1 for the different capacitive charging modes set by CAP_CHRG_CH1 bits. Note: If VBB > 19V, the device will limit the overcurrent threshold to 66A if the ILIMIT_SET_CH1 > 66A If no cap charging mode (CAP_CHRG_CH1 = 00) is used, the values are: 0x0 = 14.5A 0x1 = 18.2A 0x2 = 20.5A 0x3 = 24.2A 0x4 = 28.5A 0x5 = 30.6A 0x6 = 33.5A 0x7 = 44.3A 0x8 = 53.4A 0x9 = 66A 0xA = 76.2A Note: 0xB–0xF are not supported by design and shall never be selected. If current regulation mode (CAP_CHRG_CH1 = 10) is used, the values are: 0h = 2A 1h = 2.3A 2h = 2.7A 3h = 3.2A 4h = 3.7A 5h = 4.2A 6h = 4.6A 7h = 6.2A 8h = 7.6A 9h = 9.1A Ah = 10.6A Bh = 12.1A Ch = 13.5A Dh = 15.1A Eh = 16.7A Fh = 18.2A
3-0	ILIMIT_SET_CH1	R/W	X	These bits determine the overcurrent protection (I_OCP) threshold for channel 1 in steady state operation after the INRUSH_DURATION period expires. Note: If VBB > 19V, the device will limit the overcurrent threshold to 66A if the ILIMIT_SET_CH1 > 66A 0h = 14.5A 1h = 18.2A 2h = 20.5A 3h = 24.2A 4h = 28.5A 5h = 30.6A 6h = 33.5A 7h = 44.3A 8h = 53.4A 9h = 66A Ah = 76.2A

9.13 CH1_CONFIG Register (Offset = Fh) [Reset = XXXXh]

CH1_CONFIG is shown in Table 9-15.

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Table 9-15 CH1_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	VSNS_DIS_CH1	R/W	X	This bit determines if the VOUT VSNS ADC function for channel 1 is enabled. 0h = CH1 VOUT VSNS ADC functionality enabled 1h = CH1 VOUT VSNS ADC functionality is disabled
14	VDS_SNS_DIS_CH1	R/W	X	This bit determines if the VDS_SNS ADC function for channel 1 is enabled. 0h = CH1 VDS_SNS ADC functionality enabled 1h = CH1 VDS_SNS ADC functionality is disabled
13	ISNS_DIS_CH1	R/W	X	This bit determines if the ISNS ADC function for channel 1 is enabled. 0h = CH1 ISNS ADC functionality enabled 1h = CH1 ISNS ADC functionality is disabled
12	OUT_DIS_MASK_CH1	R/W	X	If DI_OUT_DIS_FN = 1, this bit determines if channel 1 should turn off if OUT_DIS = 1 If DI_OUT_DIS_FN = 0, then this bit has no effect 0h = CH1 will turn OFF when OUT_DIS pin is high 1h = CH1 will ignore OUT_DIS pin when high, CH1 will follow CH1_ON in active state or CH1_LH_IN in limp home state
11	RESERVED	R/W	X	Reserved
10	ISNS_SCALE_CH1	R/W	X	This bit determines the voltage scaling of the channel 1 ISNS for the input to the ADC Note: If I2T is enabled (I2T_EN_CH1 = 1) and ISNS_SCALE_CH1 = 1, the 8x voltage scaling will be applied to the I2T algorithm which will provide different I2T trip thresholds and can cause the channel to turn off at a lower I2T threshold. If this is not intended then it is recommended to only use the 8x voltage scaling option when in OL_ON_EN_CH1 = 1 mode and with I2T disabled (I2T_EN_CH1 = 0). 0h = ADC input voltage scale equals 1x 1h = ADC input voltage scale equals 8x
9	OL_ON_EN_CH1	R/W	X	This bit determines if channel 1 should enter a mode with a higher RON and a lower KSNS value to more accurately detect lower output current. Note: It is recommended to only use OL_ON_EN_CH1 = 1 mode with I2T disabled (I2T_EN_CH1 = 0). If I2T is enabled (I2T_EN_CH1 = 1) and OL_ON_EN_CH1 = 1, the lower K_SNS2 will be applied to the I2T algorithm which will provide different I2T trip thresholds and can cause the channel to turn off at a lower I2T threshold. Note: The device can only enter this mode if there are no existing faults on the channel and the output current is below I_{ENTRY_OL_ON}. 0h = KSNS1 ratio and RON = RON 1h = KSNS2 ratio and RON = RON_OL
8-7	OL_SVBB_BLANK_CH1	R/W	X	These bits determine the blanking time for open load or short to VBB faults in the OFF state for channel 1 0h = Blanking time is 0.4ms 1h = Blanking time is 1.0ms 2h = Blanking time is 2.0ms 3h = Blanking time is 4.0ms
6-5	OL_PU_STR_CH1	R/W	X	These bits determine the pull-up current (I_pu) at the VOUT1 for the off-state open load detection circuitry. 0h = I_pu is 27µA 1h = I_pu is 62µA 2h = I_pu is 128µA 3h = I_pu is 270µA
4-3	OL_SVBB_EN_CH1	R/W	X	The bits are used to enable open load and short to supply detection in OFF state. Setting to 0x02h Turns on the pull up to see if there is an open load or short to supply in the off state with an output comparator. If detected set to 0x1h to turn on a pull down to see if there is a short to VBB in the off state. 0h = Disabled 1h = Turns-on an output pulldown to differentiate Short to supply from open load. 2h = Turns on a pull-up from VBB supply to output to detect if either an open load or short-to-battery exists. 3h = Output comparator enabled, use external switches and pull-up/pull-down to detect open load or short-to-supply.
2	LATCH_CH1	R/W	X	This bit determines if channel 1 should auto-retry or latch off after an overcurrent or thermal shutdown event has occurred. 0h = Channel 1 will auto retry after tRETRY expires and THYS is reached 1h = Channel 1 latches off until SW_STATE register is written to again
1-0	SLRT_CH1	R/W	X	These bits determine the turn on and turn off slew rates for channel 1. 0h = 0.13V/µs (Rising) and 0.15V/µs (Falling) 1h = 0.22V/µs (Rising) and 0.28V/µs (Falling) 2h = 0.13V/µs (Rising) and 0.3V/µs (Falling) 3h = 0.22V/µs (Rising) and 0.47V/µs (Falling)

9.14 ADC_RESULT_CH1_I Register (Offset = 10h) [Reset = E000h]

ADC_RESULT_CH1_I is shown in Table 9-16.

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Table 9-16 ADC_RESULT_CH1_I Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	7h	Reserved
12	ISNS_CH1_ONOFF_STAT	R	0h	The bit is set to 1 if the ADC conversion of ISNS is done while the channel is ON 0h = ISNS read is done while the status of the CH1 FET is OFF 1h = ISNS read is done while the status of the CH1 FET is ON
11	ISNS_SCALE_EFF_CH1	R	0h	The bit indicates the voltage scaling factor used for the conversion 0h = 1x ISNS1 voltage scaling 1h = 8x ISNS1 voltage scaling
10	ISNS_RDY_CH1	R	0h	Making sure the ADC conversion is new from the last time this was read 0h = ADC value not updated 1h = ADC value ready since last read
9-0	ADC_RESULT_CH1_I	R	0h	ADC result (10-bits) from the conversion of the current in CH1

9.15 ADC_RESULT_CH1_T Register (Offset = 11h) [Reset = F800h]

ADC_RESULT_CH1_T is shown in Table 9-17.

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Table 9-17 ADC_RESULT_CH1_T Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	1Fh	Reserved
10	TSNS_RDY_CH1	R	0h	This bit indicates if a new ADC result for channel 1 TSNS conversion is available since the last read 0h = ADC value not updated 1h = ADC value ready since last read
9-0	ADC_RESULT_CH1_T	R	0h	10-bit ADC result from the conversion of channel 1 FET temperature (TSNS)

9.16 ADC_RESULT_CH1_V Register (Offset = 12h) [Reset = F800h]

ADC_RESULT_CH1_V is shown in Table 9-18.

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Table 9-18 ADC_RESULT_CH1_V Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	1Fh	Reserved
10	VSNS_RDY_CH1	R	0h	This bit indicates if a new ADC result for channel 1 VOUT voltage (VSNS) conversion is available since the last read 0h = ADC value not updated 1h = ADC value ready since last read
9-0	ADC_RESULT_CH1_V	R	0h	10-bit ADC result from the conversion of channel 1 VOUT voltage (VSNS)

9.17 ADC_RESULT_CH1_VDS Register (Offset = 13h) [Reset = F800h]

ADC_RESULT_CH1_VDS is shown in Table 9-19.

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Table 9-19 ADC_RESULT_CH1_VDS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	1Fh	Reserved
10	VDSSNS_RDY_CH1	R	0h	This bit indicates if a new ADC result for channel 1 VDS voltage (VDSSNS) conversion is available since the last read 0h = ADC value not updated 1h = ADC value ready since last read
9-0	ADC_RESULT_CH1_VDS	R	0h	10-bit ADC result from the conversion of channel 1 VDS voltage (VDSSNS)

9.18 I2T_CONFIG_CH1 Register (Offset = 14h) [Reset = XXXXh]

I2T_CONFIG_CH1 is shown in Table 9-20.

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Table 9-20 I2T_CONFIG_CH1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	TCLDN_CH1	R/W	X	These bits set the cool down time (or time to retry) after an I2T shutdown for Channel 1. Note: If setting 0x0 is used, the channel will remain off after an I2T shutdown with no retry. To retry in this setting, change the bits to 0.8s, 2.0s, or 4.0s options to allow the device to retry after an I2T shutdown. 0h = channel off 1h = 0.8s 2h = 2.0s 3h = 4.0s
13	DCR_CH1	R/W	X	Sets the mode of I2T operation for channel 1. If DCR = 0: the device accumulates according to I2T_TRIP = I_OUT1² x t and decrements according to I2T_TRIP = ( I_OUT1² - k x (NOM_CUR_CH1)²) x t If DCR = 1: the device accumulates and decrements according to I2T_TRIP = ( I_OUT1² - NOM_CUR_CH1²) x t. 0h = I2t Mode DCR0 1h = I2t Mode DCR1
12-11	ACC_DCR0_CH1	R/W	X	Decrement factor of accumulated energy when DCR_CH1 = 0 for the following equation: I2T_TRIP = ( I_OUT1² - k x (NOM_CUR_CH1)²) x t 0h = Decrement factor k = 0.25 1h = Decrement factor k = 0.5 2h = Decrement factor k = 1 3h = Decrement factor k = 2
10-9	SWCL_DLY_TMR_CH1	R/W	X	These bits set the timer at which Channel 1 will shut down if the IOUT current continuously exceeds the ISWCL level for the configured time. 0h = 0.06ms 1h = 0.4ms 2h = 1.0ms 3h = 2.0ms
8-7	ISWCL_CH1	R/W	X	These bits set the delayed turn off current sense value (I_SWCL,700) for channel 1. Once the IOUT current exceeds the I_SWCL,700 value, a timer starts and will turn off the channel if the current remains above the I_SWCL,700 threshold for a duration of SWCL_DLY_TMR_CH1. The threshold should be set below the current sense saturation value (I_{OUT_SAT} = K_SNS1 * I_{SNS_SAT}). The current threshold below assume R_SNS = 700Ω. To calculate the new I_SWCL,700 thresholds based on a different R_SNS value, the following equation can be used: I_SWCL,ADJ = (I_SWCL,700 * (700 / R_SNS)) / ISNS_SCALE_CH1 Note: The ISWCL_CH1 value cannot be modified when the device is in the cool down time period. 0h = 27.3A 1h = 24.6A 2h = 22.4A 3h = 18.6A
6-3	I2T_TRIP_CH1	R/W	X	These bits set the I2T trip value for Channel 1. Note: For reference the equations for the I2T trip value are below If DCR_CH1 = 0: I2T_TRIP = I_OUT1² x t If DCR_CH1 = 1: I2T = (I_OUT1² - NOM_CUR_CH1²) * t The below values assume R_SNS = 700Ω. To calculate the new I2T trip values based on a different R_SNS value, the following equation can be used: I2T_ADJ = (I2T₇₀₀ * (700 / R_SNS)²) / ISNS_SCALE_CH1 Note: The I2T_TRIP_CH1 value cannot be modified when the device is in the cool down time period. I2T settings with DCR = 0: 0h = 39A2s 1h = 59A2s 2h = 118A2s 3h = 177A2s 4h = 236A2s 5h = 295A2s 6h = 354A2s 7h = 413A2s 8h = 492A2s 9h = 570A2s Ah = 649A2s Bh = 747A2s Ch = 865A2s Dh = 983A2s Eh = 1180A2s Fh = 1573A2s I2T settings with DCR = 1: 0h = 17A2s 1h = 26A2s 2h = 52A2s 3h = 77A2s 4h = 103A2s 5h = 129A2s 6h = 155A2s 7h = 181A2s 8h = 215A2s 9h = 249A2s Ah = 284A2s Bh = 327A2s Ch = 378A2s Dh = 430A2s Eh = 516A2s Fh = 688A2s
2-0	NOM_CUR_CH1	R/W	X	These bits set the nominal current value for channel 1 for the I2T function. If the I2T function is enabled for channel 1, above this value the device will enter the I2T accumulation mode. The nominal current values below assume R_SNS = 700Ω. To calculate the new I2T trip values based on a different R_SNS value, the following equation can be used: NOM_CUR_CH1_ADJ = (NOM_CUR_CH1₇₀₀ * (700 / R_SNS)) / ISNS_SCALE_CH1 Note: The NOM_CUR_CH1 value cannot be modified when the device is in the cool down time period. 0h = 5.6A 1h = 7A 2h = 8A 3h = 9A 4h = 10.5A 5h = 12.6A 6h = 16.8A 7h = 21A

9.19 FLT_STAT_CH2 Register (Offset = 15h) [Reset = E000h]

FLT_STAT_CH2 is shown in Table 9-21.

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Table 9-21 FLT_STAT_CH2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	7h	Reserved
12	I2T_MOD_CH2	R	0h	This bit indicates if channel 2 in the I2T loop and is accumulating. When channel 2 is not in the I2T loop the value will be 0 0h = I2T is off or the channel is not in the I2T loop 1h = Channel is in the I2T loop and is accumulating
11	LATCH_STAT_CH2	R	0h	This bit indicates if channel 2 has been latch off due to an overcurrent protection or thermal shutdown fault. The bit clears when the channel is toggled off and back on. Note: This bit does not signal when a shutdown occurs due to I2T 0h = This channel is not latched off 1h = This channel is currently latched off
10	FLT_CH2	R	0h	This bit indicates if channel 2 is currently in an auto retry wait time period, latched off, or in I2T cooldown 0h = This channel is currently not in auto retry wait time, latched off state, or I2T cooldown 1h = This channel is currently in auto retry wait time, latched off state, or I2T cooldown
9	SW_STATE_STAT_CH2	R	0h	This bit indicates the current state of channel 2 no matter which mode the device is in as long as SPI is functioning 0h = CH2 is OFF 1h = CH2 is ON
8	VOUT_ERR_CH2	R	0h	This bit indicates if the drain-to-source voltage (V_DS) of channel 2 < V_{DS_LT_2V} after the channel is enabled and is out of the inrush period (if configured) for t > t_{VDS_DEGL}. 0h = The VDS voltage is correct (< 2V) when this channel is enabled 1h = The VDS voltage is incorrect (> 2V) when this channel is supposed to be enabled
7	I2T_FLT_CH2	R	0h	This bit indicates if an I2T fault has occured on channel 2. I2T_EN must be set to 1 in order for this bit indicate an I2T fault. The fault is latched and cleared when FLT_STAT_CH2 register is read and the fault condition no longer exists Note: This bit does not indicate an overcurrent protection or thermal shutdown fault 0h = no I2T fault has occurred or I2T is not enabled 1h = I2T fault has occurred on this channel
6	LPM_WAKE_CH2	R	0h	This bit indicates if channel 2 was the cause for the device to come out of AUTO_LPM or MANUAL_LPM regardless of the cause (load step, short-circuit) 0h = The device was not in LPM or this channel was not the cause the device came out of AUTO_LPM or MANUAL_LPM mode 1h = This channel was the reason the device came out of AUTO_LPM or MANUAL_LPM
5	THERMAL_SD_CH2	R	0h	This bit indicates if thermal shutdown fault has occurred on channel 2. The fault is latched and cleared when the FLT_STAT_CH2 register is read and the retry timer has expired and the channel temperature has fallen below the thermal shutdown hysteresis threshold 0h = No thermal shutdown fault has occurred on this channel 1h = A thermal shutdown fault has occurred on this channel
4	ILIMIT_CH2	R	0h	This bit indicates if an overcurrent protection fault has occurred on channel 2 The fault is latched and cleared when FLT_STAT_CH2 register is read and the fault condition no longer exists 0h = No overcurrent protection fault has occurred on this channel 1h = Overcurrent protection fault has occurred on this channel
3	SHRT_VBB_CH2	R	0h	This bit indicates if there was a short to VBB in the off-state on channel 2. The fault is latched and cleared when FLT_STAT_CH2 register is read and the fault condition no longer exists Note: SVBB_EN_CH2 must be enabled for this bit to signal short to VBB in the off state. 0h = No Short to VBB fault in off-state has occurred on this channel or short to VBB in off-state is not enabled 1h = Short to VBB fault in the off-state has occurred on this channel
2	OL_OFF_CH2	R	0h	This bit indicates if there is an open load in the off-state on channel 2. The output of channel 2 is pulled up by the OL_PULLUP_STR setting. Note: OL_OFF_EN_CH2 must be enabled for this bit to signal an open load in the off-state. 0h = No off-state open load fault has occurred on this channel or off-state open load detection in off-state is not enabled 1h = Off-state open load fault has occurred on this channel
1	RESERVED	R	0h	Reserved
0	THERMAL_WRN_CH2	R	0h	This bit indicates if the channel 2 FET temperature is above the overtemperature warning threshold. The fault is latched and cleared when FLT_STAT_CH2 register is read and the fault condition no longer exists 0h = FET temperature is below the over-temperature warning threshold in this channel 1h = FET temperature is above the over-temperature warning threshold in this channel

9.20 PWM_CH2 Register (Offset = 16h) [Reset = F000h]

PWM_CH2 is shown in Table 9-22.

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Table 9-22 PWM_CH2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	Fh	Reserved
11-9	PWM_FREQ_CH2	R/W	0h	Set the PWM frequency 0h = 0.86Hz 1h = 3.5Hz 2h = 14Hz 3h = 112Hz 4h = 224Hz 5h = 448Hz 6h = 895Hz 7h = 1765Hz
8-1	PWM_DTY_CH2	R/W	0h	These bits are used to set the duty cycle for the PWM operation for channel 2. Each bit is ~0.39% duty cycle, linearly up to 100% duty cycle
0	PWM_EN_CH2	R/W	0h	This bit enables PWM operation of channel 2. Note: The duty cycle of PWM > 200us. If fault will occur in FLT_STAT_CH2 register. PWM mode can only be enabled if CAP_CHRG_CH2[1:0] = 0 0h = Output follows CH2_ON setting 1h = Output is PWM according to duty cycle and frequency set if CH2_ON is high

9.21 ILIM_CONFIG_CH2 Register (Offset = 17h) [Reset = XXXXh]

ILIM_CONFIG_CH2 is shown in Table 9-23.

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Table 9-23 ILIM_CONFIG_CH2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R/W	X	Reserved
13-12	CAP_CHRG_CH2	R/W	X	These bits set the capacitive charging mode during the inrush period after turn on. When CAP_CHRG_CH2 = 00, these are bits are programmed as the overcurrent protection threshold during the INRUSH_DURATION_CH2 period. The channel will immediately turn off if the threshold is reached. When CAP_CHRG_CH2 = 10, these bits are programmed as the current limit regulation threshold. The channel will turn on into the current limit and will continue to regulate the current until the output is fully charged or there is a thermal shutdown event. Note: PWM and I2T is not enabled during the INRUSH_DURATION. 0h = No cap charging mode, IOCP value set by INRUSH_LIMIT_CH2 bits 1h = Not supported 2h = Current limit regulation mode, value set by INRUSH_LIMIT_CH2 bits 3h = Not supported
11	I2T_EN_CH2	R/W	X	Enables the I2T functionality for channel 2. I2T can be enabled before the channel is enabled or while it is enabled, but the I2T calculation will only start after the inrush period ends. 0h = I2T functionality not enabled 1h = I2T functionality is enabled
10-8	INRUSH_DURATION_CH2	R/W	X	These bits determine the inrush period duration during which the INRUSH_LIMIT_CH2 level applies. 0h = 0ms 1h = 2ms 2h = 4ms 3h = 6ms 4h = 10ms 5h = 20ms 6h = 50ms 7h = 100ms
7-4	INRUSH_LIMIT_CH2	R/W	X	These bits determine the inrush current limit on channel 2 for the different capacitive charging modes set by CAP_CHRG_CH2 bits. Note: If VBB > 19V, the device will limit the overcurrent threshold to 66A if the ILIMIT_SET_CH2 > 66A If no cap charging mode (CAP_CHRG_CH2 = 00) is used, the values are: 0x0 = 14.5A 0x1 = 18.2A 0x2 = 20.5A 0x3 = 24.2A 0x4 = 28.5A 0x5 = 30.6A 0x6 = 33.5A 0x7 = 44.3A 0x8 = 53.4A 0x9 = 66A 0xA = 76.2A Note: 0xB–0xF are not supported by design and shall never be selected. If current regulation mode (CAP_CHRG_CH2 = 10) is used, the values are: 0h = 2A 1h = 2.3A 2h = 2.7A 3h = 3.2A 4h = 3.7A 5h = 4.2A 6h = 4.6A 7h = 6.2A 8h = 7.6A 9h = 9.1A Ah = 10.6A Bh = 12.1A Ch = 13.5A Dh = 15.1A Eh = 16.7A Fh = 18.2A
3-0	ILIMIT_SET_CH2	R/W	X	These bits determine the overcurrent protection (I_OCP) threshold for channel 2 in steady state operation after the INRUSH_DURATION period expires. Note: If VBB > 19V, the device will limit the overcurrent threshold to 66A if the ILIMIT_SET_CH2 > 66A 0h = 14.5A 1h = 18.2A 2h = 20.5A 3h = 24.2A 4h = 28.5A 5h = 30.6A 6h = 33.5A 7h = 44.3A 8h = 53.4A 9h = 66A Ah = 76.2A

9.22 CH2_CONFIG Register (Offset = 18h) [Reset = XXXXh]

CH2_CONFIG is shown in Table 9-24.

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Table 9-24 CH2_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	VSNS_DIS_CH2	R/W	X	This bit determines if the VOUT VSNS ADC function for channel 2 is enabled. 0h = CH2 VOUT VSNS ADC functionality enabled 1h = CH2 VOUT VSNS ADC functionality is disabled
14	VDSSNS_DIS_CH2	R/W	X	This bit determines if the VDS_SNS ADC function for channel 2 is enabled. 0h = CH2 VDS_SNS ADC functionality enabled 1h = CH2 VDS_SNS ADC functionality is disabled
13	ISNS_DIS_CH2	R/W	X	This bit determines if the ISNS ADC function for channel 2 is enabled. 0h = CH2 ISNS ADC functionality enabled 1h = CH2 ISNS ADC functionality is disabled
12	OUT_DIS_MASK_CH2	R/W	X	If DI_OUT_DIS_FN = 1, this bit determines if channel 2 should turn off if OUT_DIS = 1 If DI_OUT_DIS_FN = 0, then this bit has no effect 0h = CH2 will turn OFF when OUT_DIS pin is high 1h = CH2 will ignore OUT_DIS pin when high, CH2 will follow CH2_ON in active state or CH2_LH_IN in limp home state
11	RESERVED	R/W	X	Reserved
10	ISNS_SCALE_CH2	R/W	X	This bit determines the voltage scaling of the channel 2 ISNS for the input to the ADC Note: If I2T is enabled (I2T_EN_CH2 = 1) and ISNS_SCALE_CH2 = 1, the 8x voltage scaling will be applied to the I2T algorithm which will provide different I2T trip thresholds and can cause the channel to turn off at a lower I2T threshold. If this is not intended then it is recommended to only use the 8x voltage scaling option when in OL_ON_EN_CH2 = 1 mode and with I2T disabled (I2T_EN_CH2 = 0). 0h = ADC input voltage scale equals 1x 1h = ADC input voltage scale equals 8x
9	OL_ON_EN_CH2	R/W	X	This bit determines if channel 2 should enter a mode with a higher RON and a lower KSNS value to more accurately detect lower output current. Note: It is recommended to only use OL_ON_EN_CH2 = 1 mode with I2T disabled (I2T_EN_CH2 = 0). If I2T is enabled (I2T_EN_CH2 = 1) and OL_ON_EN_CH2 = 1, the lower K_SNS2 will be applied to the I2T algorithm which will provide different I2T trip thresholds and can cause the channel to turn off at a lower I2T threshold. Note: The device can only enter this mode if there are no existing faults on the channel and the output current is below I_{ENTRY_OL_ON}. 0h = KSNS1 ratio and RON = RON 1h = KSNS2 ratio and RON = RON_OL
8-7	OL_SVBB_BLANK_CH2	R/W	X	These bits determine the blanking time for open load or short to VBB faults in the OFF state for channel 2 0h = Blanking time is 0.4ms 1h = Blanking time is 1.0ms 2h = Blanking time is 2.0ms 3h = Blanking time is 4.0ms
6-5	OL_PU_STR_CH2	R/W	X	These bits determine the pull-up current (I_pu) at the VOUT2 for the off-state open load detection circuitry. 0h = I_pu is 27µA 1h = I_pu is 62µA 2h = I_pu is 128µA 3h = I_pu is 270µA
4-3	OL_SVBB_EN_CH2	R/W	X	The bits are used to enable open load and short to supply detection in OFF state. Setting to 0x02h Turns on the pull up to see if there is an open load or short to supply in the off state with an output comparator. If detected set to 0x1h to turn on a pull down to see if there is a short to VBB in the off state. 0h = Disabled 1h = Turns-on an output pulldown to differentiate Short to supply from open load. 2h = Turns on a pull-up from VBB supply to output to detect if either an open load or short-to-battery exists. 3h = Output comparator enabled, use external switches and pull-up/pull-down to detect open load or short-to-supply.
2	LATCH_CH2	R/W	X	This bit determines if channel 2 should auto-retry or latch off after an overcurrent or thermal shutdown event has occurred. 0h = channel 2 will auto retry after tRETRY expires and THYS is reached 1h = channel 2 latches off until SW_STATE register is written to again
1-0	SLRT_CH2	R/W	X	These bits determine the turn on and turn off slew rates for channel 2. 0h = 0.13V/µs (Rising) and 0.15V/µs (Falling) 1h = 0.22V/µs (Rising) and 0.28V/µs (Falling) 2h = 0.13V/µs (Rising) and 0.3V/µs (Falling) 3h = 0.22V/µs (Rising) and 0.47V/µs (Falling)

9.23 ADC_RESULT_CH2_I Register (Offset = 19h) [Reset = E000h]

ADC_RESULT_CH2_I is shown in Table 9-25.

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Table 9-25 ADC_RESULT_CH2_I Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	7h	Reserved
12	ISNS_CH2_ONOFF_STAT	R	0h	The bit is set to 1 if the ADC conversion of ISNS is done while the channel is ON 0h = ISNS read is done while the status of the CH1 FET is OFF 1h = ISNS read is done while the status of the CH1 FET is ON
11	ISNS_SCALE_EFF_CH2	R	0h	The bit indicates the voltage scaling factor used for the conversion 0h = 1x ISNS2 voltage scaling 1h = 8x ISNS2 voltage scaling
10	ISNS_RDY_CH2	R	0h	Making sure the ADC conversion is new from the last time this was read 0h = ADC value not updated 1h = ADC value ready since last read
9-0	ADC_RESULT_CH2_I	R	0h	ADC result (10-bits) from the conversion of the current in CH2

9.24 ADC_RESULT_CH2_T Register (Offset = 1Ah) [Reset = F800h]

ADC_RESULT_CH2_T is shown in Table 9-26.

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Table 9-26 ADC_RESULT_CH2_T Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	1Fh	Reserved
10	TSNS_RDY_CH2	R	0h	This bit indicates if a new ADC result for channel 2 TSNS conversion is available since the last read 0h = ADC value not updated 1h = ADC value ready since last read
9-0	ADC_RESULT_CH2_T	R	0h	10-bit ADC result from the conversion of channel 2 FET temperature (TSNS)

9.25 ADC_RESULT_CH2_V Register (Offset = 1Bh) [Reset = F800h]

ADC_RESULT_CH2_V is shown in Table 9-27.

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Table 9-27 ADC_RESULT_CH2_V Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	1Fh	Reserved
10	VSNS_RDY_CH2	R	0h	This bit indicates if a new ADC result for channel 2 VOUT voltage (VSNS) conversion is available since the last read 0h = ADC value not updated 1h = ADC value ready since last read
9-0	ADC_RESULT_CH2_V	R	0h	10-bit ADC result from the conversion of channel 2 VOUT voltage (VSNS)

9.26 ADC_RESULT_CH2_VDS Register (Offset = 1Ch) [Reset = F800h]

ADC_RESULT_CH2_VDS is shown in Table 9-28.

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Table 9-28 ADC_RESULT_CH2_VDS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	1Fh	Reserved
10	VDSSNS_RDY_CH2	R	0h	This bit indicates if a new ADC result for channel 2 VDS voltage (VDSSNS) conversion is available since the last read 0h = ADC value not updated 1h = ADC value ready since last read
9-0	ADC_RESULT_CH2_VDS	R	0h	10-bit ADC result from the conversion of channel 2 VDS voltage (VDSSNS)

9.27 I2T_CONFIG_CH2 Register (Offset = 1Dh) [Reset = XXXXh]

I2T_CONFIG_CH2 is shown in Table 9-29.

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Table 9-29 I2T_CONFIG_CH2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	TCLDN_CH2	R/W	X	These bits set the cool down time (or time to retry) after an I2T shutdown for channel 2. Note: If setting 0x0 is used, the channel will remain off after an I2T shutdown with no retry. To retry in this setting, change the bits to 0.8s, 2.0s, or 4.0s options to allow the device to retry after an I2T shutdown. 0h = channel off 1h = 0.8s 2h = 2.0s 3h = 4.0s
13	DCR_CH2	R/W	X	Sets the mode of I2T operation for channel 2. If DCR = 0: the device accumulates according to I2T_TRIP = I_OUT2² x t and decrements according to I2T_TRIP = ( I_OUT2² - k x (NOM_CUR_CH2)²) x t If DCR = 1: the device accumulates and decrements according to I2T_TRIP = ( I_OUT2² - NOM_CUR_CH2²) x t. 0h = I2t Mode DCR0 1h = I2t Mode DCR1
12-11	ACC_DCR0_CH2	R/W	X	Decrement factor of accumulated energy when DCR_CH2 = 0 for the following equation: I2T_TRIP = ( I_OUT2² - k x (NOM_CUR_CH2)²) x t 0h = Decrement factor k = 0.25 1h = Decrement factor k = 0.5 2h = Decrement factor k = 1 3h = Decrement factor k = 2
10-9	SWCL_DLY_TMR_CH2	R/W	X	2-bits to set delayed turn-off timer for Channel 2. Sets the time after which the channel shuts down when the current exceeds ISWCL. The default values loaded from NVM. 0h = 0.06ms 1h = 0.4ms 2h = 1.0ms 3h = 2.0ms
8-7	ISWCL_CH2	R/W	X	These bits set the delayed turn off current sense value (I_SWCL,700) for channel 2. Once the I_OUT current exceeds the I_SWCL,700 value, a timer starts and will turn off the channel if the current remains above the I_SWCL,700 threshold for a duration of SWCL_DLY_TMR_CH2. The threshold should be set below the current sense saturation value (I_{OUT_SAT} = K_SNS1 * I_{SNS_SAT}). The current threshold below assume R_SNS = 700Ω. To calculate the new I_SWCL,700 thresholds based on a different R_SNS value, the following equation can be used: I_SWCL,ADJ = (I_SWCL,700 * (700 / R_SNS)) / ISNS_SCALE_CH2 Note: The ISWCL_CH2 value cannot be modified when the device is in the cool down time period. 0h = 27.3A 1h = 24.6A 2h = 22.4A 3h = 18.6A
6-3	I2T_TRIP_CH2	R/W	X	These bits set the I2T trip value for Channel 2. Note: For reference the equations for the I2T trip value are below If DCR_CH2 = 0: I2T_TRIP = I_OUT2² x t If DCR_CH2 = 1: I2T = (I_OUT2² - NOM_CUR_CH2²) * t The below values assume R_SNS = 700Ω. To calculate the new I2T trip values based on a different R_SNS value, the following equation can be used: I2T_ADJ = (I2T₇₀₀ * (700 / R_SNS)²) / ISNS_SCALE_CH2 Note: The I2T_TRIP_CH2 value cannot be modified when the device is in the cool down time period. I2T settings with DCR = 0: 0h = 39A2s 1h = 59A2s 2h = 118A2s 3h = 177A2s 4h = 236A2s 5h = 295A2s 6h = 354A2s 7h = 413A2s 8h = 492A2s 9h = 570A2s Ah = 649A2s Bh = 747A2s Ch = 865A2s Dh = 983A2s Eh = 1180A2s Fh = 1573A2s I2T settings with DCR = 1: 0h = 17A2s 1h = 26A2s 2h = 52A2s 3h = 77A2s 4h = 103A2s 5h = 129A2s 6h = 155A2s 7h = 181A2s 8h = 215A2s 9h = 249A2s Ah = 284A2s Bh = 327A2s Ch = 378A2s Dh = 430A2s Eh = 516A2s Fh = 688A2s
2-0	NOM_CUR_CH2	R/W	X	These bits set the nominal current value for channel 2 for the I2T function. If the I2T function is enabled for channel 2, above this value the device will enter the I2T accumulation mode. The nominal current values below assume R_SNS = 700Ω. To calculate the new I2T trip values based on a different R_SNS value, the following equation can be used: NOM_CUR_CH2_ADJ = (NOM_CUR_CH2₇₀₀ * (700 / R_SNS)) / ISNS_SCALE_CH2 Note: The NOM_CUR_CH2 value cannot be modified when the device is in the cool down time period. 0h = 5.6A 1h = 7A 2h = 8A 3h = 9A 4h = 10.5A 5h = 12.6A 6h = 16.8A 7h = 21A

9.28 EEPROM_PROG Register (Offset = 3Fh) [Reset = FFFCh]

EEPROM_PROG is shown in Table 9-30.

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Table 9-30 EEPROM_PROG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-2	RESERVED	R	3FFFh	Reserved
1	EEPROM_BUSY	R	0h	EEPROM programming status 0h = Device is not in EEPROM programming procedure 1h = Device is currently in EEPROM programming procedure
0	PROG_NVM	R	0h	EEPROM programming control status bit. This bit will self clear to 0 when the EEPROM programming is complete 1h = Device is programming EEPROM

9.29 TSNS_CAL_RESULT_CH1 Register (Offset = 50h) [Reset = XXXXh]

TSNS_CAL_RESULT_CH1 is shown in Table 9-31.

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Table 9-31 TSNS_CAL_RESULT_CH1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R/W	X	Reserved
9-0	TSNS_CAL_RESULT_CH1	R/W	X	10-bit ADC result from production for channel 1 FET temperature (TSNS)

9.30 TSNS_CAL_RESULT_CH2 Register (Offset = 51h) [Reset = XXXXh]

TSNS_CAL_RESULT_CH2 is shown in Table 9-32.

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Table 9-32 TSNS_CAL_RESULT_CH2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R/W	X	Reserved
9-0	TSNS_CAL_RESULT_CH2	R/W	X	10-bit ADC result from production for channel 2 FET temperature (TSNS)

9.31 CUST_REG_52 Register (Offset = 52h) [Reset = XXXXh]

CUST_REG_52 is shown in Table 9-33.

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Table 9-33 CUST_REG_52 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	CUST_REG_52_BIT15	R/W	X	Customer programmable bit
14	CUST_REG_52_BIT14	R/W	X	Customer programmable bit
13	CUST_REG_52_BIT13	R/W	X	Customer programmable bit
12	CUST_REG_52_BIT12	R/W	X	Customer programmable bit
11	CUST_REG_52_BIT11	R/W	X	Customer programmable bit
10	CUST_REG_52_BIT10	R/W	X	Customer programmable bit
9	CUST_REG_52_BIT9	R/W	X	Customer programmable bit
8	CUST_REG_52_BIT8	R/W	X	Customer programmable bit
7	CUST_REG_52_BIT7	R/W	X	Customer programmable bit
6	CUST_REG_52_BIT6	R/W	X	Customer programmable bit
5	CUST_REG_52_BIT5	R/W	X	Customer programmable bit
4	CUST_REG_52_BIT4	R/W	X	Customer programmable bit
3	CUST_REG_52_BIT3	R/W	X	Customer programmable bit
2	CUST_REG_52_BIT2	R/W	X	Customer programmable bit
1	CUST_REG_52_BIT1	R/W	X	Customer programmable bit
0	CUST_REG_52_BIT0	R/W	X	Customer programmable bit

9.32 CUST_REG_53 Register (Offset = 53h) [Reset = XXXXh]

CUST_REG_53 is shown in Table 9-34.

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Table 9-34 CUST_REG_53 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	CUST_REG_53_BIT15	R/W	X	Customer programmable bit
14	CUST_REG_53_BIT14	R/W	X	Customer programmable bit
13	CUST_REG_53_BIT13	R/W	X	Customer programmable bit
12	CUST_REG_53_BIT12	R/W	X	Customer programmable bit
11	CUST_REG_53_BIT11	R/W	X	Customer programmable bit
10	CUST_REG_53_BIT10	R/W	X	Customer programmable bit
9	CUST_REG_53_BIT9	R/W	X	Customer programmable bit
8	CUST_REG_53_BIT8	R/W	X	Customer programmable bit
7	CUST_REG_53_BIT7	R/W	X	Customer programmable bit
6	CUST_REG_53_BIT6	R/W	X	Customer programmable bit
5	CUST_REG_53_BIT5	R/W	X	Customer programmable bit
4	CUST_REG_53_BIT4	R/W	X	Customer programmable bit
3	CUST_REG_53_BIT3	R/W	X	Customer programmable bit
2	CUST_REG_53_BIT2	R/W	X	Customer programmable bit
1	CUST_REG_53_BIT1	R/W	X	Customer programmable bit
0	CUST_REG_53_BIT0	R/W	X	Customer programmable bit

9.33 CUST_REG_54 Register (Offset = 54h) [Reset = XXXXh]

CUST_REG_54 is shown in Table 9-35.

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Table 9-35 CUST_REG_54 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	CUST_REG_54_BIT15	R/W	X	Customer programmable bit
14	CUST_REG_54_BIT14	R/W	X	Customer programmable bit
13	CUST_REG_54_BIT13	R/W	X	Customer programmable bit
12	CUST_REG_54_BIT12	R/W	X	Customer programmable bit
11	CUST_REG_54_BIT11	R/W	X	Customer programmable bit
10	CUST_REG_54_BIT10	R/W	X	Customer programmable bit
9	CUST_REG_54_BIT9	R/W	X	Customer programmable bit
8	CUST_REG_54_BIT8	R/W	X	Customer programmable bit
7	CUST_REG_54_BIT7	R/W	X	Customer programmable bit
6	CUST_REG_54_BIT6	R/W	X	Customer programmable bit
5	CUST_REG_54_BIT5	R/W	X	Customer programmable bit
4	CUST_REG_54_BIT4	R/W	X	Customer programmable bit
3	CUST_REG_54_BIT3	R/W	X	Customer programmable bit
2	CUST_REG_54_BIT2	R/W	X	Customer programmable bit
1	CUST_REG_54_BIT1	R/W	X	Customer programmable bit
0	CUST_REG_54_BIT0	R/W	X	Customer programmable bit

9.34 CUST_REG_55 Register (Offset = 55h) [Reset = XXXXh]

CUST_REG_55 is shown in Table 9-36.

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Table 9-36 CUST_REG_55 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	CUST_REG_55_BIT15	R/W	X	Customer programmable bit
14	CUST_REG_55_BIT14	R/W	X	Customer programmable bit
13	CUST_REG_55_BIT13	R/W	X	Customer programmable bit
12	CUST_REG_55_BIT12	R/W	X	Customer programmable bit
11	CUST_REG_55_BIT11	R/W	X	Customer programmable bit
10	CUST_REG_55_BIT10	R/W	X	Customer programmable bit
9	CUST_REG_55_BIT9	R/W	X	Customer programmable bit
8	CUST_REG_55_BIT8	R/W	X	Customer programmable bit
7	CUST_REG_55_BIT7	R/W	X	Customer programmable bit
6	CUST_REG_55_BIT6	R/W	X	Customer programmable bit
5	CUST_REG_55_BIT5	R/W	X	Customer programmable bit
4	CUST_REG_55_BIT4	R/W	X	Customer programmable bit
3	CUST_REG_55_BIT3	R/W	X	Customer programmable bit
2	CUST_REG_55_BIT2	R/W	X	Customer programmable bit
1	CUST_REG_55_BIT1	R/W	X	Customer programmable bit
0	CUST_REG_55_BIT0	R/W	X	Customer programmable bit

9.35 CUST_REG_56 Register (Offset = 56h) [Reset = XXXXh]

CUST_REG_56 is shown in Table 9-37.

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Table 9-37 CUST_REG_56 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	CUST_REG_56_BIT15	R/W	X	Customer programmable bit
14	CUST_REG_56_BIT14	R/W	X	Customer programmable bit
13	CUST_REG_56_BIT13	R/W	X	Customer programmable bit
12	CUST_REG_56_BIT12	R/W	X	Customer programmable bit
11	CUST_REG_56_BIT11	R/W	X	Customer programmable bit
10	CUST_REG_56_BIT10	R/W	X	Customer programmable bit
9	CUST_REG_56_BIT9	R/W	X	Customer programmable bit
8	CUST_REG_56_BIT8	R/W	X	Customer programmable bit
7	CUST_REG_56_BIT7	R/W	X	Customer programmable bit
6	CUST_REG_56_BIT6	R/W	X	Customer programmable bit
5	CUST_REG_56_BIT5	R/W	X	Customer programmable bit
4	CUST_REG_56_BIT4	R/W	X	Customer programmable bit
3	CUST_REG_56_BIT3	R/W	X	Customer programmable bit
2	CUST_REG_56_BIT2	R/W	X	Customer programmable bit
1	CUST_REG_56_BIT1	R/W	X	Customer programmable bit
0	CUST_REG_56_BIT0	R/W	X	Customer programmable bit

9.36 CUST_REG_57 Register (Offset = 57h) [Reset = XXXXh]

CUST_REG_57 is shown in Table 9-38.

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Table 9-38 CUST_REG_57 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	CUST_REG_57_BIT15	R/W	X	Customer programmable bit
14	CUST_REG_57_BIT14	R/W	X	Customer programmable bit
13	CUST_REG_57_BIT13	R/W	X	Customer programmable bit
12	CUST_REG_57_BIT12	R/W	X	Customer programmable bit
11	CUST_REG_57_BIT11	R/W	X	Customer programmable bit
10	CUST_REG_57_BIT10	R/W	X	Customer programmable bit
9	CUST_REG_57_BIT9	R/W	X	Customer programmable bit
8	CUST_REG_57_BIT8	R/W	X	Customer programmable bit
7	CUST_REG_57_BIT7	R/W	X	Customer programmable bit
6	CUST_REG_57_BIT6	R/W	X	Customer programmable bit
5	CUST_REG_57_BIT5	R/W	X	Customer programmable bit
4	CUST_REG_57_BIT4	R/W	X	Customer programmable bit
3	CUST_REG_57_BIT3	R/W	X	Customer programmable bit
2	CUST_REG_57_BIT2	R/W	X	Customer programmable bit
1	CUST_REG_57_BIT1	R/W	X	Customer programmable bit
0	CUST_REG_57_BIT0	R/W	X	Customer programmable bit