SLVSHM3 November   2026 TPS2HCS05-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Package
    2. 5.2 Pinout A-version
    3. 5.3 Version B Package
    4. 5.4 Pinout B-version
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Device Functional Modes
      1. 8.3.1  State Diagram
      2. 8.3.2  Output Control
        1. 8.3.2.1 Output Control - Version A
        2. 8.3.2.2 Pin 5 Functions (DI or OUT_DIS) - Version A
        3. 8.3.2.3 Output Control - Version B
      3. 8.3.3  Output Disable Function (OUT_DIS)
      4. 8.3.4  SPI Mode Operation
        1. 8.3.4.1 SPI
        2. 8.3.4.2 Chip Select (CS or nCS)
        3. 8.3.4.3 System Clock
        4. 8.3.4.4 Serial Data In (SDI) and Serial Data Out (SDO)
        5. 8.3.4.5 CRC Error Detection and Checking of Clocks
        6. 8.3.4.6 SPI Frame Format
        7. 8.3.4.7 GLOBAL_FAULT_TYPE [15:8] Bits
        8. 8.3.4.8 SPI Watchdog Function
        9. 8.3.4.9 SPI Watchdog Operation - TPS2HCS05A-Q1
      5. 8.3.5  Fault Reporting
      6. 8.3.6  SLEEP
      7. 8.3.7  CONFIG/ACTIVE
      8. 8.3.8  LIMP_HOME State (Version A Only)
        1. 8.3.8.1 LIMP HOME State Exceptions
      9. 8.3.9  Battery Supply Input (VBB) Under-Voltage
        1. 8.3.9.1 VBB During Short-to-Ground
      10. 8.3.10 LOW POWER MODE (LPM) States
        1. 8.3.10.1 MANUAL_LPM State
          1. 8.3.10.1.1 System Wakeup from MANUAL_LPM
          2. 8.3.10.1.2 Automatic Exit from MANUAL_LPM
        2. 8.3.10.2 AUTO_LPM State
          1. 8.3.10.2.1 System Wakeup from AUTO_LPM
          2. 8.3.10.2.2 Automatic Exit from AUTO_LPM
    4. 8.4 Feature Description
      1. 8.4.1 Protection Mechanisms
        1. 8.4.1.1 Overcurrent Protection
          1. 8.4.1.1.1 Inrush Period - Overcurrent Protection
            1. 8.4.1.1.1.1 No Capacitive Charging - CAP_CHRG_CHx [1:0] = 00
            2. 8.4.1.1.1.2 Current Limit Regulation Capacitive Charging Mode - CAP_CHRG_CHx [1:0] = 10
          2. 8.4.1.1.2 Overcurrent Protection - Steady State Operation
          3. 8.4.1.1.3 Programmable Fuse Protection
          4. 8.4.1.1.4 Immediate Shutdown Overcurrent Protection (IOCP)
          5. 8.4.1.1.5 Auto retry and latch-off behavior
            1. 8.4.1.1.5.1 Auto retry behavior - No capacitive charging mode (CAP_CHRG_CHx = 00)
            2. 8.4.1.1.5.2 Latch-off Behavior - No Capacitive Charging Mode (CAP_CHRG_CHx = 00)
            3. 8.4.1.1.5.3 Auto Retry Behavior - Current Limit Regulation Charging Mode (CAP_CHRG_CHx = 10)
            4. 8.4.1.1.5.4 Latch-off Behavior - Current Limit Regulation Capactive Charging Mode (CAP_CHRG_CHx = 10)
        2. 8.4.1.2 Thermal Shutdown
          1. 8.4.1.2.1 Relative Thermal Shutdown (TREL)
          2. 8.4.1.2.2 Absolute Thermal Shutdown (TABS)
        3. 8.4.1.3 Reverse Battery
      2. 8.4.2 Diagnostic Mechanisms
        1. 8.4.2.1 Integrated ADC
        2. 8.4.2.2 Digital Current Sense Output
        3. 8.4.2.3 Output Voltage Measurement
        4. 8.4.2.4 MOSFET Temperature Measurement
        5. 8.4.2.5 Drain-to-Source Voltage (VDS) Measurement
        6. 8.4.2.6 VBB Voltage Measurement
        7. 8.4.2.7 VOUT Short-to-Battery and Open-Load
          1. 8.4.2.7.1 Measurement with Channel Output (FET) Enabled
          2. 8.4.2.7.2 Detection with Channel Output Disabled
            1. 8.4.2.7.2.1 Off-State Open Load Detection
            2. 8.4.2.7.2.2 Off-State Short-to-Battery Detection
            3. 8.4.2.7.2.3 Distinguishing Between Open Load and Short-to-Battery Faults
      3. 8.4.3 EEPROM Overview
        1. 8.4.3.1 EEPROM Programming Procedure
        2. 8.4.3.2 Customer Defined Programmable Registers
  10. 9 TPS2HCS05-Q1 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Thermal Considerations
        2. 10.2.2.2 Configuring the Capacitive Charging Mode
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • PWC|18
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.6 SLEEP

The TPS2HCS05-Q1 device offers a SLEEP state where the device is placed into an ultra-low current consumption state. When the device is in SLEEP state, both channels are OFF, registers are cleared, and all digital circuits are powered off. The device transitions to this state if VBB < VBB_UVLO and VDD < VDD_UVLO. The device can manually be put into SLEEP state by pulling DI/OUT_DIS Low and writing a 1 to the SLEEP bit in the SLEEP register. After the device enters SLEEP mode, the DI/OUT_DIS pin can be released.

The device can be woken from the SLEEP state through the CSN pin going low. There are two methods to wake the device up from SLEEP through the CSN pin:

  1. Pulse the CSN pin low for t < tREADY
  2. Hold the CSN pin low for at least tREADY and continue to hold CSN pin low through the first SPI transaction

Both methods above result in the device waking up without a SPI_ERR fault. A psuedo-SPI transaction can be used to satisfy method number 1 if the psuedo-SPI transaction is completed in t < tREADY. Figure 8-15 below shows examples of the two proper wake-up scenarios which results in no SPI_ERR fault and one improper wake-up scenario which results in a SPI_ERR fault.

Upon wake-up from SLEEP state, the values in the registers are set to the reset values detailed in the register map below. Additionally, the FLT pin is asserted low and the POR, VDD_UVLO, and VBB_UVLO fault bits are asserted and are cleared when the GLOBAL_FAULT_TYPE register is read if none of these faults currently exist when read.

TPS2HCS05-Q1 Startup Communication TimingFigure 8-15 Startup Communication Timing