SLVS331J December   2000  – August 2024 TPS3813

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Dissipation Ratings
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 VDD Hysteresis
        2. 7.3.1.2 VDD Glitch Immunity
      2. 7.3.2 User-Programmable Watchdog Timer (WDI)
      3. 7.3.3 RESET Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VIT)
      2. 7.4.2 Above Power-On Reset But Less Than Threshold (VPOR < VDD < VIT)
      3. 7.4.3 Below Power-On Reset (VDD < VPOR)
    5. 7.5 Programming
      1. 7.5.1 Implementing Window-Watchdog Settings
      2. 7.5.2 Programmable Window-Watchdog by Using an External Capacitor
      3. 7.5.3 Lower Boundary Calculation
      4. 7.5.4 Watchdog Software Considerations
      5. 7.5.5 Power-Up Considerations
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Related Links
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The TPS3813xxx family of supervisory circuits provide circuit initialization and timing supervision, primarily for DSPs and processor-based systems.

During power on, RESET is asserted when supply voltage (VDD) becomes higher than 1.1V. Thereafter, the supervisory circuit monitors VDD and keeps RESET active as long as VDD remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time,
td = 25ms typical, starts after VDD has risen above the threshold voltage (VIT). When the supply voltage drops below the threshold voltage (VIT), the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage (VIT) set by an internal voltage divider.

For safety critical applications the TPS3813xxx family incorporates a so-called window-watchdog with programmable delay and window ratio. The upper limit of the watchdog time-out can be set by either connecting WDT to GND, VDD, or using an external capacitor. The lower limit and thus the window ratio is set by connecting WDR to GND or VDD. The supervised processor now needs to trigger the TPS3813xxx within this window not to assert a RESET.

The product spectrum is designed for supply voltages of 2.5V, 3V, 3.3V, and 5V. The circuits are available in a 6-pin SOT-23 package.

The TPS3813xxx devices are characterized for operation over a temperature range of –40°C to 85°C.

Device Information
PART NUMBERPACKAGE (1)BODY SIZE (NOM) (2)
TPS3813xxxSOT-23 (6)2.90mm × 1.60mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.