SLVSB90C January   2012  – November 2023 TPS40170-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  LDO Linear Regulators and Enable
      2. 6.3.2  Input Undervoltage Lockout (UVLO)
      3. 6.3.3  Equations for Programming the Input UVLO
      4. 6.3.4  Overcurrent Protection and Short-Circuit Protection (OCP and SCP)
      5. 6.3.5  Oscillator and Voltage Feed-Forward
        1. 6.3.5.1 Calculating the Timing Resistance (RRT)
      6. 6.3.6  Feed-Forward Oscillator Timing Diagram
      7. 6.3.7  Soft-Start and Fault-Logic
        1. 6.3.7.1 Soft-Start During Overcurrent Fault
        2. 6.3.7.2 Equations for Soft-Start and Restart Time
      8. 6.3.8  Overtemperature Fault
      9. 6.3.9  Tracking
      10. 6.3.10 Adaptive Drivers
      11. 6.3.11 Start-Up Into Pre-Biased Output
      12. 6.3.12 31
      13. 6.3.13 Power Good (PGOOD)
      14. 6.3.14 PGND and AGND
      15. 6.3.15 Bootstrap Capacitor
      16. 6.3.16 Bypass and Filtering
    4. 6.4 Device Functional Modes
      1. 6.4.1 Frequency Synchronization
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Select A Switching Frequency
        2. 7.2.2.2  Inductor Selection (L1)
        3. 7.2.2.3  Output Capacitor Selection (C9)
        4. 7.2.2.4  Peak Current Rating of Inductor
        5. 7.2.2.5  Input Capacitor Selection (C1, C6)
        6. 7.2.2.6  MOSFET Switch Selection (Q1, Q2)
        7. 7.2.2.7  Timing Resistor (R7)
        8. 7.2.2.8  UVLO Programming Resistors (R2, R6)
        9. 7.2.2.9  Bootstrap Capacitor (C7)
        10. 7.2.2.10 VIN Bypass Capacitor (C18)
        11. 7.2.2.11 VBP Bypass Capacitor (C19)
        12. 7.2.2.12 SS Timing Capacitor (C15)
        13. 7.2.2.13 ILIM Resistor (R19, C17)
        14. 7.2.2.14 SCP Multiplier Selection (R5)
        15. 7.2.2.15 Feedback Divider (R10, R11)
        16. 7.2.2.16 Compensation: (R4, R13, C13, C14, C21)
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Bootstrap Resistor
      2. 7.3.2 SW-Node Snubber Capacitor
      3. 7.3.3 Input Resistor
      4. 7.3.4 LDRV Gate Capacitor
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4.1 Frequency Synchronization

The TPS40170-Q1 device has three modes.

  • Primary mode: In this mode, the primary- or secondary-selector pin, (M/S) is connected to VIN. The SYNC pin emits a stream of pulses at the same frequency as the PWM switching frequency. The pulse stream at the SYNC pin is of 50% duty cycle and the same amplitude as VVBP. Also, the falling edge of the voltage on SYNC pin is synchronized with the rising edge of HDRV.
  • Secondary–180° mode: In this mode, the M/S pin is connected to GND. The SYNC pin of the TPS40170-Q1 device accepts a synchronization clock signal, and HDRV is synchronized with the rising edge of the incoming synchronization clock.
  • Secondary–0° mode: In this mode, the M/S pin is left open. The SYNC pin of the TPS40170-Q1 device accepts a synchronization clock signal, and HDRV is synchronized with the falling edge of the incoming synchronization clock.

The two secondary modes can be synchronized to an external clock through the SYNC pin. They are shown in Figure 6-18. The synchronization frequency must be within ±30% of its programmed free-running frequency.

GUID-95911048-813A-4E3F-BE35-616482C464C7-low.gifFigure 6-18 Frequency Synchronization Waveforms in Different Modes

TPS40170-Q1 device provides a smooth transition for the SYNC clock-signal loss in secondary mode. In secondary mode, a synchronization clock signal is provided externally through the SYNC pin to the device. The switching frequency is synchronized to the external SYNC clock signal. If for some reason the external clock signal is missing, the device switching frequency is automatically overridden by a transition frequency which is 0.7 times its programmed free-running frequency. This transition time is approximately 20 μs. After that, the device switching frequency is changed to its programmed free-running frequency. Figure 6-19 shows this process.

GUID-617A546C-B514-4A9E-A047-10E39B77F09C-low.gifFigure 6-19 Transition for SYNC Clock Signal Missing (for Secondary–180° Mode)
Note:

When the device is operating in the primary mode with duty ratio around 50%, PWM jittering can occur. Always configure the device into the secondary mode by either connecting the M/S pin to GND or leaving it floating if primary mode is not used.

When the external SYNC clock signal is used for synchronization, limit the maximum slew rate of the clock signal to 10 V/µs to avoid potential PWM jittering,and connect the SYNC pin to the external clock signal through a 5-kΩ resistor.