SLVSB90C January   2012  – November 2023 TPS40170-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  LDO Linear Regulators and Enable
      2. 6.3.2  Input Undervoltage Lockout (UVLO)
      3. 6.3.3  Equations for Programming the Input UVLO
      4. 6.3.4  Overcurrent Protection and Short-Circuit Protection (OCP and SCP)
      5. 6.3.5  Oscillator and Voltage Feed-Forward
        1. 6.3.5.1 Calculating the Timing Resistance (RRT)
      6. 6.3.6  Feed-Forward Oscillator Timing Diagram
      7. 6.3.7  Soft-Start and Fault-Logic
        1. 6.3.7.1 Soft-Start During Overcurrent Fault
        2. 6.3.7.2 Equations for Soft-Start and Restart Time
      8. 6.3.8  Overtemperature Fault
      9. 6.3.9  Tracking
      10. 6.3.10 Adaptive Drivers
      11. 6.3.11 Start-Up Into Pre-Biased Output
      12. 6.3.12 31
      13. 6.3.13 Power Good (PGOOD)
      14. 6.3.14 PGND and AGND
      15. 6.3.15 Bootstrap Capacitor
      16. 6.3.16 Bypass and Filtering
    4. 6.4 Device Functional Modes
      1. 6.4.1 Frequency Synchronization
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Select A Switching Frequency
        2. 7.2.2.2  Inductor Selection (L1)
        3. 7.2.2.3  Output Capacitor Selection (C9)
        4. 7.2.2.4  Peak Current Rating of Inductor
        5. 7.2.2.5  Input Capacitor Selection (C1, C6)
        6. 7.2.2.6  MOSFET Switch Selection (Q1, Q2)
        7. 7.2.2.7  Timing Resistor (R7)
        8. 7.2.2.8  UVLO Programming Resistors (R2, R6)
        9. 7.2.2.9  Bootstrap Capacitor (C7)
        10. 7.2.2.10 VIN Bypass Capacitor (C18)
        11. 7.2.2.11 VBP Bypass Capacitor (C19)
        12. 7.2.2.12 SS Timing Capacitor (C15)
        13. 7.2.2.13 ILIM Resistor (R19, C17)
        14. 7.2.2.14 SCP Multiplier Selection (R5)
        15. 7.2.2.15 Feedback Divider (R10, R11)
        16. 7.2.2.16 Compensation: (R4, R13, C13, C14, C21)
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Bootstrap Resistor
      2. 7.3.2 SW-Node Snubber Capacitor
      3. 7.3.3 Input Resistor
      4. 7.3.4 LDRV Gate Capacitor
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

These specifications apply for –40°C ≤ TA ≤ +125°C, VVIN = 12 V, unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
INPUT SUPPLY
VVINInput voltage range4.560V
ISDShutdown currentVENABLE < 100 mV12.5µA
IQQOperating current, drivers not switchingVENABLE ≥ 2 V, fSW = 300 kHz4.5mA
ENABLE
VDISENABLE pin voltage to disable the device100mV
VENENABLE pin voltage to enable the device600mV
IENABLEENABLE pin source current300nA
8-V AND 3.3-V REGULATORS
VVBP8-V regulator output voltageVENABLE ≥ 2 V, 8.2 V < VVIN ≤ 60 V,
0 mA < IIN < 20 mA		7.88.08.3V
VDO8-V regulator dropout voltage,
VVIN-VVBP		4.5 < VVIN ≤ 8.2 V, VEN ≥ 2 V,
IIN = 10 mA		110200mV
VVDD3.3-V regulator output voltageVENABLE ≥ 2 V, 4.5 V < VVIN ≤ 60 V,
0 mA < IIN < 5 mA		3.223.33.42V
FIXED AND PROGRAMMABLE UVLO
VUVLOProgrammable UVLO ON voltage (at UVLO pin)VENABLE ≥ 2 V878900919mV
IUVLOHysteresis current out of UVLO pinVENABLE ≥ 2 V , UVLO pin > VUVLO4.0656.2µA
VBPONVBP turnon voltageVENABLE ≥ 2 V, UVLO pin > VUVLO3.854.4V
VBPOFFVBP turnoff voltage3.64.05
VBPHYSVBP UVLO Hysteresis voltage180400mV
REFERENCE
VREFReference voltage (+ input of the error amplifier)TJ = 25°C, 4.5 V < VVIN ≤ 60 V594600606mV
–40°C ≤ TJ ≤ 125°C, 4.5 V < VVIN ≤ 60 V591600609
OSCILLATOR
fSWSwitching frequencyRange (typical)100600kHz
RRT = 100 kΩ, 4.5 V < VVIN ≤ 60 V90100110
RRT = 31.6 kΩ, 4.5 V < VVIN ≤ 60 V270300330
RRT = 14.3 kΩ, 4.5 V < VVIN ≤ 60 V540600660
VVALLEYValley voltage0.711.2V
KPWM(1)PWM gain (VVIN / VRAMP)4.5 V < VVIN ≤ 60 V141516V/V
PWM AND DUTY CYCLE
tON(min)(1)Minimum controlled pulseVVIN = 4.5 V, fSW = 300 kHz100150ns
VVIN = 12 V, fSW = 300 kHz75100
VVIN = 60 V, fSW = 300 kHz5080
tOFF(max)(1)Minimum OFF timeVVIN = 12V, fSW = 300 kHz170250ns
DMAX(1)Maximum duty cyclefSW = 100 kHz, 4.5 V < VVIN ≤ 60 V95%
fSW = 300 kHz, 4.5 V < VVIN ≤ 60 V91%
fSW = 600 kHz, 4.5 V < VVIN ≤ 60 V82%
ERROR AMPLIFIER
GBWP(1)Gain bandwidth product71013MHz
AOL(1)Open-loop gain809095dB
IIBInput bias current100nA
IEAOPOutput source currentVVFB = 0 V2mA
IEAOMOutput sink currentVVFB = 1 V2mA
PROGRAMMABLE SOFT START
ISS(source,start)Soft-start source currentVSS < 0.5 V, VSS = 0.25 V425262µA
ISS(source,normal)Soft-start source currentVSS > 0.5 V, VSS = 1.5 V9.311.613.9µA
ISS(sink)Soft-start sink currentVSS = 1.5 V0.771.051.33µA
VSS(fltH)SS pin HIGH voltage during fault (OC or thermal) reset timing2.382.52.61V
VSS(fltL)SS pin LOW voltage during fault (OC or thermal) reset timing235300375mV
VSS(steady_state)SS pin voltage during steady-state3.253.33.5V
VSS(offst)Initial offset voltage from SS pin to error amplifier input525650775mV
TRACKING
VTRK(ctrl)(1)Range of TRK which overrides VREF4.5 V < VIN ≤ 60 V0600mV
SYNCHRONIZATION (PRIMARY/SECONDARY)
VMSTRM/S pin voltage in primary mode3.9VINV
VSLV(0)M/S pin voltage in secondary 0° mode1.251.75V
VSLV(180)M/S pin voltage in secondary 180° mode00.75V
ISYNC(in)SYNC pin pulldown currentM/S configured as secondary- 0° or
secondary-180°		81114µA
VSYNC(in_high)SYNC pin input high-voltage level2V
VSYNC(in_low)SYNC pin input low-voltage level0.8V
tSYNC(high_min)Minimum SYNC high pulse duration4050ns
tSYNC(low_min)Minimum SYNC low pulse duration4050ns
GATE DRIVERS
RHDHIHigh-side driver pullup resistanceCLOAD = 2.2 nF, IDRV = 300 mA, TA = –40°C to 125°C1.372.644Ω
RHDLOHigh-side driver pulldown resistance1.082.44Ω
RLDHILow-side driver pullup resistance1.372.44Ω
RLDLOLow-side driver pulldown resistance0.441.11.7Ω
tNON-OVERLAP1Time delay between HDRV fall and LDRV riseCLOAD = 2.2 nF,
VHDRV = 2 V, VLDRV = 2 V		50ns
tNON-OVERLAP2Time delay between HDRV rise and LDRV fall60
OVERCURRENT PROTECTION (LOW-SIDE MOSFET SENSING)
IILIMILIM pin source current4.5 V < VIN < 60 V, TA = 25°C99.7510.45µA
4.5 V < VIN < 60 V, TA = –40°C to 125°C712
IILIM,(ss)ILIM pin source current during soft-start4.5 V < VIN < 60 V, TA = 25°C15µA
4.5 V < VIN < 60 V, TA = –40°C to 125°C712
IILIM, Tc(1)Temperature coefficient of ILIM current4.5 V < VIN < 60 V1400ppm
VILIM(1)ILIM pin voltage operating range4.5 V < VIN < 60 V50300mV
OCPTHOvercurrent protection threshold (voltage across low-side FET for detecting overcurrent)RILIM = 10 kΩ, IILIM = 10 µA
(VILIM = 100 mV)		–110–100–84mV
SHORT CIRCUIT PROTECTION HIGH-SIDE MOSFET SENSING)
VLDRV(max)LDRV pin maximum voltage during calibrationRLDRV = open300360mV
AOC3Multiplier factor to set the SCP based on OCP level setting at the ILIM pinRLDRV = 10 kΩ2.753.23.6V/V
AOC7RLDRV = open6.47.257.91V/V
AOC15RLDRV = 20 kΩ13.916.418V/V
THERMAL SHUTDOWN
TSD,set(1)Thermal shutdown set threshold4.5 V < VVIN < 60 V155165175°C
TSD,reset(1)Thermal shutdown reset threshold125135145°C
Thyst(1)Thermal shutdown hysteresis30°C
POWER GOOD
VOVFB pin voltage upper limit for power good4.5 V < VVIN < 60 V627647670mV
VUVFB pin voltage lower limit for power good527552570
VPG,HYSTPower good hysteresis voltage at FB pin8.52032
VPG(out)PGOOD pin voltage when FB pin voltage > VOV or < VUV, IPGD = 2 mA100mV
VPG(np)PGOOD pin voltage when device power is removedVVIN is open, 10-kΩ to VEXT = 5 V11.5V
BOOT DIODE
VDFWDBootstrap diode forward voltageI = 20 mA0.50.70.9V
RBOOT-SWDischarge resistor from BOOT to SW1MΩ
(1) Not production tested.