The device settings can be configured when in programming mode before the device begins power conversion. When in programming mode, the switching frequency, current limit, internal compensation, soft-start rate, and FCCM enable/disable can be configured. Once the voltage on the EN pin exceeds the EN threshold and power conversion begins, these registers are read only. Configuration settings will be lost if device is allowed to go back into low-power shutdown mode.

When the TPS542A50 detects an individual fault of OCP, OT, OV, or UV, the STATUS register (0x01) asserts a logic high or "1" in its respective bit field. The asserted fault bits will remain high even after the fault is removed. To clear the asserted fault bits, cycle power to the device, or write a logic high to the bit field of the STATUS register for the desired bits to be cleared. Bits can be cleared individually or all at once by writing “0xDE.” In the case of both OCP and OT bits detection, they are designed to automatically clear one another. For example, in the case of an OCP fault followed by an OT fault, the OCP will initially assert a logic high, but when the OT is encountered, the OCP will automatically clear to a logic low or “0”, and only the OT fault bit will remain asserted as a logic high. If the events are encountered in the reverse order, then only the OCP will remain asserted as a logic high and the OT fault bit will be cleared to a logic low.