SNVSBC0C September   2020  – December 2021 TPS542A50

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Adjustable Undervoltage Lockout
      2. 7.3.2  Input and VREG Undervoltage Lockout Protection
      3. 7.3.3  Voltage Reference and Setting the Output Voltage
      4. 7.3.4  Remote Sense Function
      5. 7.3.5  Switching Frequency
      6. 7.3.6  Voltage Control Mode Internal Compensation
      7. 7.3.7  Soft Start and Prebiased Output Start-up
      8. 7.3.8  Power Good
      9. 7.3.9  Overvoltage and Undervoltage Protection
      10. 7.3.10 Overcurrent Protection
      11. 7.3.11 High-Side FET Throttling
      12. 7.3.12 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse-Frequency Modulation Eco-mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
      3. 7.4.3 Soft Start
    5. 7.5 Programming
      1. 7.5.1 I2C Address Selection
      2. 7.5.2 Powering Device Into Programming Mode
      3. 7.5.3 Device Configuration
      4. 7.5.4 Output Voltage Adjustment
    6. 7.6 Pin-Strap Programming
    7. 7.7 Register Maps
      1. 7.7.1 ID Register (Offset = 0x0) [reset = 0x21]
      2. 7.7.2 STATUS Register (Offset = 0x1) [reset = 0x0]
      3. 7.7.3 VOUT_ADJ1 Register (Offset = 0x2) [reset = 0x0]
      4. 7.7.4 VOUT_ADJ2 Register (Offset = 0x3) [reset = 0x0]
      5. 7.7.5 CONFIG1 Register (Offset = 0x4) [reset = 0x0B]
      6. 7.7.6 CONFIG2 Register (Offset = 0x5) [reset = 0x2D]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Full Analog Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2  Output Voltage Calculation
          3. 8.2.1.2.3  Switching Frequency Selection
          4. 8.2.1.2.4  Inductor Selection
          5. 8.2.1.2.5  Input Capacitor Selection
          6. 8.2.1.2.6  Bootstrap Capacitor Selection
          7. 8.2.1.2.7  R-C Snubber and VIN Pin High-Frequency Bypass
          8. 8.2.1.2.8  Output Capacitor Selection
          9. 8.2.1.2.9  Response to a Load Transient
          10. 8.2.1.2.10 Pin-Strap Setting
        3. 8.2.1.3 Application Curves
        4. 8.2.1.4 Typical Application Circuits
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Fusion Digital Power™ Designer Tool
        2. 11.1.1.2 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = -40℃ to 150℃ (unless otherwise noted)
PARAMETER(1) TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY (PVIN, AVIN PINS)
VIN PVIN and AVIN supply range 4 12 18 V
IQ Shutdown current EN < 0.4 V 17 µA
PFM Mode current VIN = 12 V, VOUT = 1 V, EN > 1.2 V, no switching, VRSP > 5*VVSET 1800
ENABLE and UVLO (EN PIN)
VEN Enable threshold: ON/OFF Rising and falling 1.2 V
IEN Enable input current Enable threshold – 50 mV –0.6 µA
Enable threshold + 50 mV –5
UVLO (AVIN, PVIN PINS)
AVIN, PVIN UVLO rising threshold 3.75 3.85 4 V
UVLO falling threshold 3.50 3.6 3.7
Hysteresis 0.25
INTERNAL REGULATOR, POWER STAGE (VREG PIN)
VVREG LDO output voltage LDO output current = 0A 4.3 4.7 4.96 V
VVREG LDO output voltage LDO output current = 30mA 4.7 V
Output current limit VVREG = 4.7V 120 170 220 mA
Nominal output current fsw = 2.2 MHz, output current = 15 A, VVREG = 4.7V 30 mA
VREG(UVLO) UVLO rising yhreshold 2.8 V
UVLO falling threshold 2.6
UVLO hysteresis 0.2
CONTROL REFERENCE VOLTAGE (SREF PIN)
VSREF SREF output voltage Tolerance included in RSP/RSN accuracy 1.2 V
ISREF SREF current sourcing capability Resistance > 6 kΩ 200 µA
OUTPUT VOLTAGE REGULATION ACCURACY
Output Voltage Accuracy; Vout = 1V Total internal accuracy, measured at the RSP and RSN pins = 5*VSET, VSET = 0.2V, –40 to 150°C -15 15 mV
Output Voltage Accuracy; Vout =1V Total internal accuracy, measured at the RSP and RSN pins = 5*VSET, VSET = 0.2V, –40 to 125°C -13 13 mV
Output Voltage Accuracy; Vout = 1V  Total internal accuracy, measured at the RSP and RSN pins = 5*VSET, VSET = 0.2V, 0 to 105°C  -11.0 9.0 mV
Output Voltage Accuracy; Vout = 0.8V Total internal accuracy, measured at the RSP and RSN pins = 5*VSET, VSET = 0.16V, –40 to 150°C -15 15 mV
Output Voltage Accuracy; Vout = 1.2V Total internal accuracy, measured at the RSP and RSN pins = 5*VSET, VSET = 0.24V, –40 to 150°C -15 15 mV
Output Voltage Accuracy; Vout = 5.5V (1) Total internal accuracy, measured at the RSP and RSN pins = 5*VSET, VSET = 1.1V, –40 to 150°C -30 30 mV
REMOTE SENSE AMPLIFIER
Unity gain bandwidth (1) 7 MHz
Open loop gain (1) 83 dB
Slew rate (1) 2.5 V/us
Input common mode range (1) -0.05 1.1 V
Vos Input offset voltage (RSA and EA combined offset trim)  (1) 0.25 mV
SWITCHING FREQUENCY
FSW_1MHz Switching frequency 1MHz  RFSEL = 35.7 kΩ or Short 900 1000 1100 kHz
FSW_400kHz Switching frequency 400kHz RFSEL = 7.5 kΩ -10 +15 %
FSW_600kHz Switching frequency 600kHz RFSEL = 18.2 kΩ -10 +15 %
FSW_800kHz Switching frequency 800kHz RFSEL = 26.1kΩ -10 +15 %
FSW_1.2MHz Switching frequency 1.2MHz RFSEL = 47.5 kΩ -9 +11 %
FSW_2MHz Switching frequency 2MHz RFSEL = 61.9 kΩ -10 +15 %
FSW_2.2MHz Switching frequency 2.2MHz RFSEL = 78.7 kΩ -10 +15 %
Minimum On-Time 12 ns
Minimum Off-Time 85 ns
SYNC
VIH(SYNC) High-level input voltage EN = High 1.35 V
VIL(SYNC) Low-level input voltage 0.8 V
Sync input minimum pulse width 50 ns
ΔfSYNC SYNC pin frequency range from fSW –10% 15%
VIH(SYNC)-PROG High-level input voltage to enter programming mode when EN = 0V EN = Low 1.35 V
I2C COMMUNICATION (SDA, SCL)
VIH(I2C) High-level input voltage 1.35 V
VIL(I2C) Low-level input voltage 0.8 V
IIH(I2C) High-level input leakage current –5 5  µA
IIL(I2C) Low-level input leakage current –5 5 µA
VOL(I2C) Low-level output voltage IPULLUP = 20mA 0.4 V
IPULLUP Current through pull-up resistor 20 mA
fCLK(I2C) I2C operating frequency 10 1000 kHz
CPin Typical pin capacitance for each line (SDA, SCL) 10 pF
POWER STAGE
Rds(on)1 Main high-side MOSFET on-resistance VVREG = 4.7 V, TJ = 25°C 9.1 mΩ
Rds(on)2 Main Low-side MOSFET on-resistance VVREG = 4.7 V, TJ = 25°C 2.6 mΩ
Tdt(L-H) Dead-time between low-side off and high-side on transition VREG = 4.7V, TJ = 25°C 10 ns
Tdt(H-L) Dead-time between high-side off and low-side on transition VREG = 4.7V, TJ = 25°C 10 ns
CURRENT SENSE AND PROTECTION
IS1 OC limit HS FET 20 A
IS2 OC limit LS FET 6 RILIM = 61.9 kΩ 17.60 20 22 A
OC limit LS FET 5 RILIM = 47.5 kΩ 14.78 16.5 18.48
OC limit LS FET 4 RILIM = 35.7 kΩ 11.56 13 15.62
OC limit LS FET 3 RILIM = 26.1 kΩ 9.26 10.5 13.56
OC limit LS FET 2 RILIM = 18.2 kΩ 6.96 8 11.60
OC limit LS FET 1 RILIM = 7.5 kΩ 4.66 5.5 9.60
IS2 Negative OC limit LS FET -8.5 A
IS2 Zero-cross detection comparator trip point  135 mA
SOFT-START COUNTER
tSS SS setting 1: 2.0MHz CLK VVSET = 0.1 V to 0.28 V 0.45 ms
SS setting 2: 1.0MHz CLK VVSET = 0.1 V to 0.28 V 0.9
SS setting 3: 0.5MHz CLK VVSET = 0.1 V to 0.28 V 1.8
SS setting 4: 0.25MHz CLK VVSET = 0.1 V to 0.28 V 3.6
OUTPUT ADJUSTMENT
Output voltage adjust upper limit  10 %
Output voltage adjust lower limit –20 %
Step size 0.5 %
INTERNAL BOOTSTRAP SWITCH
Forward voltage VVREG(BOOT), IF = 10 mA, TA = 25°C 0.16 0.3 V
OUTPUT VOLTAGE OVERSHOOT REDUCTION
POWER-ON DELAY
Power-on delay time From EN to SS; VIN > 4 V 500 us
POWER GOOD and OV/UV WARNING
VRSP OV warning level RSP rising (fault) 105 110 115 % 5*VVSET
OV warning level RSP falling (reset) 100 105 109
UV warning level RSP falling (fault) 87 90 93.5
UV warning level RSP rising (reset) 91 95 99
PGD delay time Delay from SS finish to PGD high 500 µs
Rds(on)PGFET PGD FET On Resistance, IPGOOD =5mA 4.1 5.8 9.1 Ω
OUTPUT OVERVOLTAGE PROTECTION (OVP)
VRSP OVP trip level RSP rising (fault), VVSET ≤ 1.04 V 110 115 120 % 5*VVSET
OVP reset level RSP falling 76 80 84
OVP delay 100 ns
OUPUT UNDERVOLTAGE PROTECTION (UVP)
VRSP UVP detect voltage 76 80 84 % 5*VSET
UV delay 100 ns
THERMAL SHUTDOWN
TSDN Shutdown temperature(1) 155 165 0C
Hysteresis(1) 15 0C
(1) Specified by design. Not production tested.