SNVSBC0C September   2020  – December 2021 TPS542A50

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Adjustable Undervoltage Lockout
      2. 7.3.2  Input and VREG Undervoltage Lockout Protection
      3. 7.3.3  Voltage Reference and Setting the Output Voltage
      4. 7.3.4  Remote Sense Function
      5. 7.3.5  Switching Frequency
      6. 7.3.6  Voltage Control Mode Internal Compensation
      7. 7.3.7  Soft Start and Prebiased Output Start-up
      8. 7.3.8  Power Good
      9. 7.3.9  Overvoltage and Undervoltage Protection
      10. 7.3.10 Overcurrent Protection
      11. 7.3.11 High-Side FET Throttling
      12. 7.3.12 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse-Frequency Modulation Eco-mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
      3. 7.4.3 Soft Start
    5. 7.5 Programming
      1. 7.5.1 I2C Address Selection
      2. 7.5.2 Powering Device Into Programming Mode
      3. 7.5.3 Device Configuration
      4. 7.5.4 Output Voltage Adjustment
    6. 7.6 Pin-Strap Programming
    7. 7.7 Register Maps
      1. 7.7.1 ID Register (Offset = 0x0) [reset = 0x21]
      2. 7.7.2 STATUS Register (Offset = 0x1) [reset = 0x0]
      3. 7.7.3 VOUT_ADJ1 Register (Offset = 0x2) [reset = 0x0]
      4. 7.7.4 VOUT_ADJ2 Register (Offset = 0x3) [reset = 0x0]
      5. 7.7.5 CONFIG1 Register (Offset = 0x4) [reset = 0x0B]
      6. 7.7.6 CONFIG2 Register (Offset = 0x5) [reset = 0x2D]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Full Analog Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2  Output Voltage Calculation
          3. 8.2.1.2.3  Switching Frequency Selection
          4. 8.2.1.2.4  Inductor Selection
          5. 8.2.1.2.5  Input Capacitor Selection
          6. 8.2.1.2.6  Bootstrap Capacitor Selection
          7. 8.2.1.2.7  R-C Snubber and VIN Pin High-Frequency Bypass
          8. 8.2.1.2.8  Output Capacitor Selection
          9. 8.2.1.2.9  Response to a Load Transient
          10. 8.2.1.2.10 Pin-Strap Setting
        3. 8.2.1.3 Application Curves
        4. 8.2.1.4 Typical Application Circuits
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Fusion Digital Power™ Designer Tool
        2. 11.1.1.2 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.2.1.2.5 Input Capacitor Selection

The TPS542A50 requires a high-quality, ceramic, type X5R or X7R, input decoupling capacitor with a value of at least 1 μF of effective capacitance on the PVIN pin, relative to PGND. The power stage input decoupling capacitance (effective capacitance at the PVIN and PGND pins) must be sufficient to supply the high switching currents demanded when the high-side MOSFET switches on, while providing minimal input voltage ripple as a result. This effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple to the device during full load. The input ripple current can be calculated by Equation 4.

Equation 4. GUID-05E2E3ED-861A-4324-84EF-22FD60DC2AC4-low.gif

The minimum input capacitance and ESR values for a given input voltage ripple specification, VIN(ripple), are shown in Equation 5. The input ripple is composed of a capacitive portion, VIN(RIPPLE_CAP), and a resistive portion, VIN(RIPPLE_ESR).

Equation 5. GUID-14824BD1-A5ED-4206-97B5-D19786CECDF0-low.gif

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor must also be selected with the DC bias taken into account. For this example design, a ceramic capacitor with at least a 25-V voltage rating is required to support the maximum input voltage. For this design, allow 0.1-V input ripple for VIN(RIPPLE_CAP), and 0.1-V input ripple for VIN(RIPPLE_ESR). UsingEquation 5, the minimum input capacitance for this design is 6.4 µF, and the maximum ESR is 8.5 mΩ. In a real application, it is recommended to use a combination of small capacitors such as 0.1 μF and larger value 10-μF or 22-μF ceramic capacitors in parallel for the power stage.