The PVIN pins are the power inputs to the main half bridge and AVIN is the power
input to the controller.
Connect AVIN and PVIN together on the PCB. It is important that these pins are
at the same voltage potential because the controller feedforward block uses this
voltage information in the modulator to increase transient performance. For
AVIN, it is best to use RC filter from PVIN such as 10-Ω and 100 nF.
To minimize the power loop inductance for the half bridge, place the bypassing
capacitors as close as possible to the PVIN pins on the converter. When using a
multilayer PCB (more than two layers), the power loop inductance is minimized by
having the return path to the input capacitor small and directly underneath the
first layer as shown below. Loop inductance is reduced due to flux cancellation
as the return current is directly underneath and flowing in the opposite
direction.
Place the bias capacitor for VREG pin as close as possible to the pin as shown
below.
The resistor divider network for SREF and VSET needs to placed as close as
possible to the pins. Limit the high frequency noise source coupling onto these
components.
RSP and RSN signals are best to route parallel to the load sense location. It is
recommended to limit high frequency noise source coupling onto these
traces.
PGND thermal vias: It is recommended to add vias under and outside the IC of
PGND plane as shown below.
AGND thermal vias: It is recommended to add at least two vias under the IC of
AGND plane as shown below.
AGND plane can be routed as a separate island in an internal layer. AGND can
connect as a net tied to PGND between the two thermal grounds under the IC as
shown below.
Total PCB area can be routed in 17 mm by 14 mm as shown below. See the Using the TPS542A50EVM-059 user's guide for more
details.